This patch converts the Geode GX2 boards to CAR.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Joseph Smith <joe@settoplinux.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

4 files changed, 14 insertions, 26 deletions

diff --git a/src/mainboard/olpc/btest/Kconfig b/src/mainboard/olpc/btest/Kconfig
index 9ed3a33a36..3b95a8ba50 100644
--- a/src/mainboard/olpc/btest/Kconfig
+++ b/src/mainboard/olpc/btest/Kconfig
@@ -4,8 +4,9 @@ config BOARD_OLPC_BTEST
 	select CPU_AMD_GX2
 	select NORTHBRIDGE_AMD_GX2
 	select SOUTHBRIDGE_AMD_CS5536
-	select ROMCC
 	select UDELAY_TSC
+	select USE_DCACHE_RAM
+	select USE_PRINTK_IN_CAR
 	select HAVE_PIRQ_TABLE
 	select BOARD_ROMSIZE_KB_256
 
diff --git a/src/mainboard/olpc/btest/romstage.c b/src/mainboard/olpc/btest/romstage.c
index a0e71d8584..a6d675fadd 100644
--- a/src/mainboard/olpc/btest/romstage.c
+++ b/src/mainboard/olpc/btest/romstage.c
@@ -2,7 +2,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
 #include "lib/ramtest.c"
@@ -132,16 +131,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 #include "northbridge/amd/gx2/pll_reset.c"
 #include "cpu/amd/model_gx2/cpureginit.c"
 #include "cpu/amd/model_gx2/syspreinit.c"
-static void msr_init(void)
-{
-	__builtin_wrmsr(0x1808,  0x10f3bf00, 0x22fffc02);
-
-	__builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
-        __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
-
-        __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
-        __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
-}
+#include "cpu/amd/model_lx/msrinit.c"
 
 static void gpio_init(void)
 {
@@ -155,7 +145,7 @@ static void gpio_init(void)
 	outl(m, GPIOL_EVENTS_ENABLE);
 }
 
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl [] = {
 		{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
@@ -175,6 +165,9 @@ static void main(unsigned long bist)
 	uart_init();
 	console_init();
 
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
 	pll_reset();
 
 	cpuRegInit();
diff --git a/src/mainboard/olpc/rev_a/Kconfig b/src/mainboard/olpc/rev_a/Kconfig
index fd8a712564..6c097c1135 100644
--- a/src/mainboard/olpc/rev_a/Kconfig
+++ b/src/mainboard/olpc/rev_a/Kconfig
@@ -4,8 +4,9 @@ config BOARD_OLPC_REV_A
 	select CPU_AMD_GX2
 	select NORTHBRIDGE_AMD_GX2
 	select SOUTHBRIDGE_AMD_CS5536
-	select ROMCC
 	select UDELAY_TSC
+	select USE_DCACHE_RAM
+	select USE_PRINTK_IN_CAR
 	select HAVE_PIRQ_TABLE
 	select BOARD_ROMSIZE_KB_256
 
diff --git a/src/mainboard/olpc/rev_a/romstage.c b/src/mainboard/olpc/rev_a/romstage.c
index a0e71d8584..a6d675fadd 100644
--- a/src/mainboard/olpc/rev_a/romstage.c
+++ b/src/mainboard/olpc/rev_a/romstage.c
@@ -2,7 +2,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
 #include "lib/ramtest.c"
@@ -132,16 +131,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 #include "northbridge/amd/gx2/pll_reset.c"
 #include "cpu/amd/model_gx2/cpureginit.c"
 #include "cpu/amd/model_gx2/syspreinit.c"
-static void msr_init(void)
-{
-	__builtin_wrmsr(0x1808,  0x10f3bf00, 0x22fffc02);
-
-	__builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
-        __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
-
-        __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
-        __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
-}
+#include "cpu/amd/model_lx/msrinit.c"
 
 static void gpio_init(void)
 {
@@ -155,7 +145,7 @@ static void gpio_init(void)
 	outl(m, GPIOL_EVENTS_ENABLE);
 }
 
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl [] = {
 		{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
@@ -175,6 +165,9 @@ static void main(unsigned long bist)
 	uart_init();
 	console_init();
 
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
 	pll_reset();
 
 	cpuRegInit();