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authorRonald G. Minnich <rminnich@gmail.com>2006-07-21 19:21:38 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-07-21 19:21:38 +0000
commitda7ee9fa07b4eaebd6e16faa678d814d9ba03ef1 (patch)
treec86847785bdcd547d0121314f6021c4dc5482f26 /src/mainboard/olpc/rev_a
parent35befb75ead1b4bc34ef351bec2a411a3ee70519 (diff)
These changes incorporate steve goodrich'es fixes, and one bug that is
disabled. cs5536: add new entires for SB control etc. cs5536.c: chip_enabled function moved to chip_init, so it only gets run once. IRQ setup improved gx2def.h: new defines added vr.h: new file, with new def's for virtual register control. mainboard config.lb: new entries added for nb and sb control. chipsetinit.c: new controls added -- I forget all the details :-) grphinit.c: new function added northbridge.c: new IRQ control added. FlashChipSetup added, controlled by chip info setupflash struct member. Currently, if enabled, this hangs OLPC in linux PCI scan. chip.h: new struct members added for unwanted device enable, flash setup git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/olpc/rev_a')
-rw-r--r--src/mainboard/olpc/rev_a/Config.lb6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/mainboard/olpc/rev_a/Config.lb b/src/mainboard/olpc/rev_a/Config.lb
index db80ccd02a..0ab8e1e3ac 100644
--- a/src/mainboard/olpc/rev_a/Config.lb
+++ b/src/mainboard/olpc/rev_a/Config.lb
@@ -125,6 +125,7 @@ config chip.h
chip northbridge/amd/gx2
register "irqmap" = "0xaa5b"
+ register "setupflash" = "0"
device apic_cluster 0 on
chip cpu/amd/model_gx2
device apic 0 on end
@@ -147,7 +148,10 @@ chip northbridge/amd/gx2
device pci f.2 on end # IDE Controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
- device pci f.5 on end # UHCI
+ device pci f.5 on end # EHCI
+ register "unwanted_vpci[0]" = "0x80007E00" # USB/UDC
+ register "unwanted_vpci[1]" = "0x80007F00" # USB/OTG
+ register "unwanted_vpci[2]" = "0" # End of list has a zero
end
end
end