diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-02-04 12:57:05 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-08 11:00:45 +0000 |
| commit | a1024ac933e74fa2c607e991be4ee705215f563d (patch) | |
| tree | 4f664d6a1b54fc470ae8c6bffccee0e58254a372 /src/mainboard/ocp | |
| parent | 8c905a82f5d07ae7936114d392ec897756c0df9d (diff) | |
mb/ocp/wedge100s: Fix devicetree
Match devicetree what's present and in use.
Tested on wedge100s:
All PCI devices show up.
Change-Id: I669d059da1876ed669793db8c7eb1b96b481cb4c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/31228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/ocp')
| -rw-r--r-- | src/mainboard/ocp/wedge100s/devicetree.cb | 29 |
1 files changed, 24 insertions, 5 deletions
diff --git a/src/mainboard/ocp/wedge100s/devicetree.cb b/src/mainboard/ocp/wedge100s/devicetree.cb index bbea89e558..48410bae08 100644 --- a/src/mainboard/ocp/wedge100s/devicetree.cb +++ b/src/mainboard/ocp/wedge100s/devicetree.cb @@ -4,10 +4,26 @@ chip soc/intel/fsp_broadwell_de end device domain 0 on device pci 00.0 on end # SoC router - device pci 14.0 on end # xHCI Controller - device pci 19.0 on end # Gigabit LAN Controller - device pci 1d.0 on end # EHCI Controller - device pci 1f.0 on + device pci 01.0 on # PCIe x1 + # Intel i210t + end + device pci 02.0 on # PCIe x1 + # QuickData Technology + end + device pci 02.2 on # PCIe x1 + # Intel X552 10 GbE SFP+ + end + device pci 03.0 on end # PEG 16x + device pci 05.0 on end # Vtd + device pci 05.1 on end # IIO Hotplug + device pci 05.2 on end # IIO + device pci 05.4 on end # PIC + device pci 14.0 off end # xHCI Controller + device pci 1c.0 on # PCH PCIe Gen2 x4 + # BCM56960 Switch ASIC + end + device pci 1d.0 on end # PCH EHCI Controller + device pci 1f.0 on # LPC chip drivers/pc80/tpm device pnp 0c31.0 on end end @@ -47,6 +63,9 @@ chip soc/intel/fsp_broadwell_de end # LPC Bridge device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus Controller - device pci 1f.5 on end # SATA Controller + device pci 1f.5 off end # SATA Controller + device pci 1f.6 on # Thermal Management Controller + # DON'T DISABLE, CRASHES FSP MR2 + end end end |