mb/*/*: Remove BROADWELL_DE boards

Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.

Change-Id: I3d9b6bb48bfd15c0182448f774e9af1e0c944fd5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

38 files changed, 0 insertions, 2245 deletions

diff --git a/src/mainboard/ocp/Kconfig b/src/mainboard/ocp/Kconfig
deleted file mode 100644
index b748129e81..0000000000
--- a/src/mainboard/ocp/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if VENDOR_OCP
-
-choice
-	prompt "Mainboard model"
-
-source "src/mainboard/ocp/*/Kconfig.name"
-
-endchoice
-
-source "src/mainboard/ocp/*/Kconfig"
-
-config MAINBOARD_VENDOR
-	string
-	default "Open Compute Project"
-
-endif # VENDOR_OCP
diff --git a/src/mainboard/ocp/Kconfig.name b/src/mainboard/ocp/Kconfig.name
deleted file mode 100644
index f5d8d0a8eb..0000000000
--- a/src/mainboard/ocp/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config VENDOR_OCP
-	bool "Open Compute Project"
diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig
deleted file mode 100644
index 7d85bbba70..0000000000
--- a/src/mainboard/ocp/monolake/Kconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-if BOARD_OCP_MONOLAKE
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select SOC_INTEL_FSP_BROADWELL_DE
-	select BOARD_ROMSIZE_KB_16384
-	select HAVE_ACPI_TABLES
-	select HAVE_OPTION_TABLE
-	select INTEGRATED_UART if FSP_PACKAGE_DEFAULT
-	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
-	select SERIRQ_CONTINUOUS_MODE
-	select MAINBOARD_USES_IFD_GBE_REGION
-	select MAINBOARD_HAS_LPC_TPM
-	select MAINBOARD_HAS_TPM1
-	select IPMI_KCS
-	select VPD
-
-config VBOOT
-	select VBOOT_VBNV_CMOS
-	select VBOOT_NO_BOARD_SUPPORT
-	select GBB_FLAG_DISABLE_LID_SHUTDOWN
-	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
-	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
-	select GBB_FLAG_DISABLE_FWMP
-
-config INTEGRATED_UART
-	def_bool n
-
-config MAINBOARD_DIR
-	string
-	default "ocp/monolake"
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Mono Lake"
-
-config IRQ_SLOT_COUNT
-	int
-	default 18
-
-config CBFS_SIZE
-	hex
-	default 0x00200000
-
-config VIRTUAL_ROM_SIZE
-	hex
-	default 0x1000000
-
-config DRIVERS_UART_8250IO
-	def_bool n
-
-config FSP_PACKAGE_DEFAULT
-	bool "Configure defaults for the Intel FSP package"
-	default n
-
-config FMDFILE
-	string
-	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
-
-config IPMI_KCS_REGISTER_SPACING
-	default 4
-
-endif # BOARD_OCP_MONOLAKE
diff --git a/src/mainboard/ocp/monolake/Kconfig.name b/src/mainboard/ocp/monolake/Kconfig.name
deleted file mode 100644
index d8284257d8..0000000000
--- a/src/mainboard/ocp/monolake/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_OCP_MONOLAKE
-	bool "Mono Lake"
diff --git a/src/mainboard/ocp/monolake/Makefile.inc b/src/mainboard/ocp/monolake/Makefile.inc
deleted file mode 100644
index b6a26b0147..0000000000
--- a/src/mainboard/ocp/monolake/Makefile.inc
+++ /dev/null
@@ -1,17 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2012 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-ramstage-y += irqroute.c
-ramstage-y += ipmi.c
diff --git a/src/mainboard/ocp/monolake/acpi/mainboard.asl b/src/mainboard/ocp/monolake/acpi/mainboard.asl
deleted file mode 100644
index 62944ef353..0000000000
--- a/src/mainboard/ocp/monolake/acpi/mainboard.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Device (PWRB)
-{
-	Name(_HID, EisaId("PNP0C0C"))
-}
diff --git a/src/mainboard/ocp/monolake/acpi/platform.asl b/src/mainboard/ocp/monolake/acpi/platform.asl
deleted file mode 100644
index 7ffae2e6e0..0000000000
--- a/src/mainboard/ocp/monolake/acpi/platform.asl
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* The APM port can be used for generating software SMIs */
-
-OperationRegion (APMP, SystemIO, 0xb2, 2)
-Field (APMP, ByteAcc, NoLock, Preserve)
-{
-	APMC, 8,	// APM command
-	APMS, 8		// APM status
-}
-
-/* Port 80 POST */
-
-OperationRegion (POST, SystemIO, 0x80, 1)
-Field (POST, ByteAcc, Lock, Preserve)
-{
-	DBG0, 8
-}
-
-Name(\APC1, Zero) // IIO IOAPIC
-
-Name(\PICM, Zero) // IOAPIC/8259
-
-Method(_PIC, 1)
-{
-	Store(Arg0, PICM)
-}
-
-/* The _PTS method (Prepare To Sleep) is called before the OS is
- * entering a sleep state. The sleep state number is passed in Arg0
- */
-
-Method(_PTS,1)
-{
-}
-
-/* The _WAK method is called on system wakeup */
-
-Method(_WAK,1)
-{
-	Return(Package(){0,0})
-}
diff --git a/src/mainboard/ocp/monolake/acpi_tables.c b/src/mainboard/ocp/monolake/acpi_tables.c
deleted file mode 100644
index 0197def7a7..0000000000
--- a/src/mainboard/ocp/monolake/acpi_tables.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- * Copyright (C) 2015-2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/ioapic.h>
-#include <soc/acpi.h>
-#include <soc/iomap.h>
-
-extern const unsigned char AmlCode[];
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	u32 i;
-
-	current = acpi_create_madt_lapics(current);
-
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 8,
-		IOXAPIC1_BASE_ADDRESS, 0);
-	set_ioapic_id((u8 *)IOXAPIC1_BASE_ADDRESS, 8);
-
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 9,
-		IOXAPIC2_BASE_ADDRESS, 24);
-	set_ioapic_id((u8 *)IOXAPIC2_BASE_ADDRESS, 9);
-
-	current = acpi_madt_irq_overrides(current);
-
-	for (i = 0; i < 16; i++)
-		current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, i, 0xD, 1);
-
-	return current;
-}
diff --git a/src/mainboard/ocp/monolake/board.fmd b/src/mainboard/ocp/monolake/board.fmd
deleted file mode 100644
index d0265e464d..0000000000
--- a/src/mainboard/ocp/monolake/board.fmd
+++ /dev/null
@@ -1,22 +0,0 @@
-FLASH@0xff000000 0x1000000 {
-	SI_ALL@0x0 0x800000 {
-		SI_DESC@0x0 0x1000
-		SI_ME@0x1000 0x7ff000
-	}
-	SI_BIOS@0x800000 0x800000 {
-		FMAP@0x0 0x1000
-		RW_MISC@0x1000 0x9000 {
-			RW_ELOG@0x0 0x4000
-			RW_VPD@0x4000 0x2000
-			RW_NVRAM@0x6000 0x2000
-		}
-		UNUSED@0xa000 0x4000 {
-			# This only exists to satisfy tools that
-			# specifically look for RO_VPD.
-			RO_VPD@0x0 0x4000
-		}
-		RW_MRC_CACHE@0xE000 0x10000
-		CONSOLE@0x1E000 0x10000
-		COREBOOT(CBFS)@0x2E000 0x7d2000
-	}
-}
diff --git a/src/mainboard/ocp/monolake/board_info.txt b/src/mainboard/ocp/monolake/board_info.txt
deleted file mode 100644
index 22c62cafd7..0000000000
--- a/src/mainboard/ocp/monolake/board_info.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-Board name: Mono Lake
-Category: server
-ROM protocol: SPI
-ROM socketed: yes
-Release year: 2016
diff --git a/src/mainboard/ocp/monolake/cmos.layout b/src/mainboard/ocp/monolake/cmos.layout
deleted file mode 100644
index 3aaa56b569..0000000000
--- a/src/mainboard/ocp/monolake/cmos.layout
+++ /dev/null
@@ -1,120 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-# -----------------------------------------------------------------
-entries
-
-#start-bit length  config config-ID    name
-#0            8       r       0        seconds
-#8            8       r       0        alarm_seconds
-#16           8       r       0        minutes
-#24           8       r       0        alarm_minutes
-#32           8       r       0        hours
-#40           8       r       0        alarm_hours
-#48           8       r       0        day_of_week
-#56           8       r       0        day_of_month
-#64           8       r       0        month
-#72           8       r       0        year
-# -----------------------------------------------------------------
-# Status Register A
-#80           4       r       0        rate_select
-#84           3       r       0        REF_Clock
-#87           1       r       0        UIP
-# -----------------------------------------------------------------
-# Status Register B
-#88           1       r       0        auto_switch_DST
-#89           1       r       0        24_hour_mode
-#90           1       r       0        binary_values_enable
-#91           1       r       0        square-wave_out_enable
-#92           1       r       0        update_finished_enable
-#93           1       r       0        alarm_interrupt_enable
-#94           1       r       0        periodic_interrupt_enable
-#95           1       r       0        disable_clock_updates
-# -----------------------------------------------------------------
-# Status Register C
-#96           4       r       0        status_c_rsvd
-#100          1       r       0        uf_flag
-#101          1       r       0        af_flag
-#102          1       r       0        pf_flag
-#103          1       r       0        irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104          7       r       0        status_d_rsvd
-#111          1       r       0        valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112          8       r       0        diag_rsvd1
-
-# -----------------------------------------------------------------
-0          120       r       0        reserved_memory
-#120        264       r       0        unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#390          2       r       0        unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-#392          3       r       0        unused
-395          4       e       6        debug_level
-#399          1       r       0        unused
-
-# coreboot config options: cpu
-400          1       e       2        hyper_threading
-#401          7       r       0        unused
-
-# coreboot config options: southbridge
-408          1       e       1        nmi
-409          2       e       7        power_on_after_fail
-#411          5       r       0        unused
-416          128      r      0        vbnv
-
-# MRC Scrambler Seed values
-896         32        r       0        mrc_scrambler_seed
-928         32        r       0        mrc_scrambler_seed_s3
-
-# coreboot config options: check sums
-984         16       h       0        check_sum
-#1000        24       r       0        amd_reserved
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     0     Emergency
-6     1     Alert
-6     2     Critical
-6     3     Error
-6     4     Warning
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-7     0     Disable
-7     1     Enable
-7     2     Keep
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 415 984
diff --git a/src/mainboard/ocp/monolake/devicetree.cb b/src/mainboard/ocp/monolake/devicetree.cb
deleted file mode 100644
index 26c95d5d67..0000000000
--- a/src/mainboard/ocp/monolake/devicetree.cb
+++ /dev/null
@@ -1,25 +0,0 @@
-chip soc/intel/fsp_broadwell_de
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-	device domain 0 on
-		device pci 00.0 on end # SoC router
-		device pci 02.2 off end # IOU0 port C, 10GbE
-		device pci 02.3 off end # IOU0 port D, 10GbE
-		device pci 14.0 on end # xHCI Controller
-		device pci 19.0 on end # Gigabit LAN Controller
-		device pci 1d.0 on end # EHCI Controller
-		device pci 1f.0 on
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-			chip drivers/ipmi		# BMC KCS
-				device pnp ca2.0 on end
-				register "bmc_i2c_address" = "0x20"
-			end
-		end # LPC Bridge
-		device pci 1f.2 on end # SATA Controller
-		device pci 1f.3 on end # SMBus Controller
-		device pci 1f.5 on end # SATA Controller
-	end
-end
diff --git a/src/mainboard/ocp/monolake/dsdt.asl b/src/mainboard/ocp/monolake/dsdt.asl
deleted file mode 100644
index 1248703266..0000000000
--- a/src/mainboard/ocp/monolake/dsdt.asl
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2015-2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	0x02,		// DSDT revision: ACPI v2.0 and up
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x20110725	// OEM revision
-)
-{
-	#include "acpi/platform.asl"
-
-	Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 })
-	Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 })
-
-	Scope (\_SB)
-	{
-		Device (PCI0)
-		{
-			#include <acpi/southcluster.asl>
-			#include <acpi/pcie1.asl>
-		}
-
-		Name (PRUN, Package() {
-			Package() { 0x0008FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0008FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0008FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0008FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x0009FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0009FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0009FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0009FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x000AFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x000AFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x000AFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x000AFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x000BFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x000BFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x000BFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x000BFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x000CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x000CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x000CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x000CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x000DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x000DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x000DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x000DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x000EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x000EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x000EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x000EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x000FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x000FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x000FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x000FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x0010FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0010FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0010FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0010FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x0011FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0011FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0011FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0011FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x0012FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0012FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0012FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0012FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x0013FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0013FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0013FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0013FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x0014FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0014FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0014FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0014FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x0016FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0016FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0016FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0016FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x0017FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0017FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0017FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0017FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x0018FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0018FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0018FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0018FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x0019FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0019FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0019FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0019FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x001CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x001CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x001CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x001CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x001DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x001DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x001DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x001DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x001EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x001EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x001EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x001EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x001FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x001FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x001FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x001FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-		})
-
-		Name (ARUN, Package() {
-			Package() { 0x0008FFFF, 0, 0, 16 },
-			Package() { 0x0008FFFF, 1, 0, 17 },
-			Package() { 0x0008FFFF, 2, 0, 18 },
-			Package() { 0x0008FFFF, 3, 0, 19 },
-
-			Package() { 0x0009FFFF, 0, 0, 16 },
-			Package() { 0x0009FFFF, 1, 0, 17 },
-			Package() { 0x0009FFFF, 2, 0, 18 },
-			Package() { 0x0009FFFF, 3, 0, 19 },
-
-			Package() { 0x000AFFFF, 0, 0, 16 },
-			Package() { 0x000AFFFF, 1, 0, 17 },
-			Package() { 0x000AFFFF, 2, 0, 18 },
-			Package() { 0x000AFFFF, 3, 0, 19 },
-
-			Package() { 0x000BFFFF, 0, 0, 16 },
-			Package() { 0x000BFFFF, 1, 0, 17 },
-			Package() { 0x000BFFFF, 2, 0, 18 },
-			Package() { 0x000BFFFF, 3, 0, 19 },
-
-			Package() { 0x000CFFFF, 0, 0, 16 },
-			Package() { 0x000CFFFF, 1, 0, 17 },
-			Package() { 0x000CFFFF, 2, 0, 18 },
-			Package() { 0x000CFFFF, 3, 0, 19 },
-
-			Package() { 0x000DFFFF, 0, 0, 16 },
-			Package() { 0x000DFFFF, 1, 0, 17 },
-			Package() { 0x000DFFFF, 2, 0, 18 },
-			Package() { 0x000DFFFF, 3, 0, 19 },
-
-			Package() { 0x000EFFFF, 0, 0, 16 },
-			Package() { 0x000EFFFF, 1, 0, 17 },
-			Package() { 0x000EFFFF, 2, 0, 18 },
-			Package() { 0x000EFFFF, 3, 0, 19 },
-
-			Package() { 0x000FFFFF, 0, 0, 16 },
-			Package() { 0x000FFFFF, 1, 0, 17 },
-			Package() { 0x000FFFFF, 2, 0, 18 },
-			Package() { 0x000FFFFF, 3, 0, 19 },
-
-			Package() { 0x0010FFFF, 0, 0, 16 },
-			Package() { 0x0010FFFF, 1, 0, 17 },
-			Package() { 0x0010FFFF, 2, 0, 18 },
-			Package() { 0x0010FFFF, 3, 0, 19 },
-
-			Package() { 0x0011FFFF, 0, 0, 16 },
-			Package() { 0x0011FFFF, 1, 0, 17 },
-			Package() { 0x0011FFFF, 2, 0, 18 },
-			Package() { 0x0011FFFF, 3, 0, 19 },
-
-			Package() { 0x0012FFFF, 0, 0, 16 },
-			Package() { 0x0012FFFF, 1, 0, 17 },
-			Package() { 0x0012FFFF, 2, 0, 18 },
-			Package() { 0x0012FFFF, 3, 0, 19 },
-
-			Package() { 0x0013FFFF, 0, 0, 16 },
-			Package() { 0x0013FFFF, 1, 0, 17 },
-			Package() { 0x0013FFFF, 2, 0, 18 },
-			Package() { 0x0013FFFF, 3, 0, 19 },
-
-			Package() { 0x0014FFFF, 0, 0, 16 },
-			Package() { 0x0014FFFF, 1, 0, 17 },
-			Package() { 0x0014FFFF, 2, 0, 18 },
-			Package() { 0x0014FFFF, 3, 0, 19 },
-
-			Package() { 0x0016FFFF, 0, 0, 16 },
-			Package() { 0x0016FFFF, 1, 0, 17 },
-			Package() { 0x0016FFFF, 2, 0, 18 },
-			Package() { 0x0016FFFF, 3, 0, 19 },
-
-			Package() { 0x0017FFFF, 0, 0, 16 },
-			Package() { 0x0017FFFF, 1, 0, 17 },
-			Package() { 0x0017FFFF, 2, 0, 18 },
-			Package() { 0x0017FFFF, 3, 0, 19 },
-
-			Package() { 0x0018FFFF, 0, 0, 16 },
-			Package() { 0x0018FFFF, 1, 0, 17 },
-			Package() { 0x0018FFFF, 2, 0, 18 },
-			Package() { 0x0018FFFF, 3, 0, 19 },
-
-			Package() { 0x0019FFFF, 0, 0, 16 },
-			Package() { 0x0019FFFF, 1, 0, 17 },
-			Package() { 0x0019FFFF, 2, 0, 18 },
-			Package() { 0x0019FFFF, 3, 0, 19 },
-
-			Package() { 0x001CFFFF, 0, 0, 16 },
-			Package() { 0x001CFFFF, 1, 0, 17 },
-			Package() { 0x001CFFFF, 2, 0, 18 },
-			Package() { 0x001CFFFF, 3, 0, 19 },
-
-			Package() { 0x001DFFFF, 0, 0, 16 },
-			Package() { 0x001DFFFF, 1, 0, 17 },
-			Package() { 0x001DFFFF, 2, 0, 18 },
-			Package() { 0x001DFFFF, 3, 0, 19 },
-
-			Package() { 0x001EFFFF, 0, 0, 16 },
-			Package() { 0x001EFFFF, 1, 0, 17 },
-			Package() { 0x001EFFFF, 2, 0, 18 },
-			Package() { 0x001EFFFF, 3, 0, 19 },
-
-			Package() { 0x001FFFFF, 0, 0, 16 },
-			Package() { 0x001FFFFF, 1, 0, 17 },
-			Package() { 0x001FFFFF, 2, 0, 18 },
-			Package() { 0x001FFFFF, 3, 0, 19 },
-		})
-
-		Device (UNC0)
-		{
-			Name (_HID, EisaId ("PNP0A03"))
-			Name (_UID, 0x3F)
-			Method (_BBN, 0, NotSerialized)
-			{
-				Return (0xff)
-			}
-
-			Name (_ADR, 0x00)
-			Method (_STA, 0, NotSerialized)
-			{
-				Return (0xf)
-			}
-
-			Name (_CRS, ResourceTemplate ()
-			{
-				WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
-					0x0000,             // Granularity
-					0x00FF,             // Range Minimum
-					0x00FF,             // Range Maximum
-					0x0000,             // Translation Offset
-					0x0001,             // Length
-					,, )
-			})
-
-			Method (_PRT, 0, NotSerialized)
-			{
-				If (LEqual (PICM, Zero))
-				{
-					Return (PRUN)
-				}
-
-				Return (ARUN)
-			}
-		}
-	}
-
-	#include "acpi/mainboard.asl"
-}
diff --git a/src/mainboard/ocp/monolake/fadt.c b/src/mainboard/ocp/monolake/fadt.c
deleted file mode 100644
index 5af6056b49..0000000000
--- a/src/mainboard/ocp/monolake/fadt.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/acpi.h>
-
-void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
-{
-	acpi_header_t *header = &(fadt->header);
-
-	acpi_fill_in_fadt(fadt, facs, dsdt);
-
-	/* Platform specific customizations go here */
-
-	header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
-}
diff --git a/src/mainboard/ocp/monolake/ipmi.c b/src/mainboard/ocp/monolake/ipmi.c
deleted file mode 100644
index 3f178dc2cc..0000000000
--- a/src/mainboard/ocp/monolake/ipmi.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2019 Wiwynn Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <stdint.h>
-#include <drivers/ipmi/ipmi_kcs.h>
-#include <console/console.h>
-#include "ipmi.h"
-
-int is_ipmi_clear_cmos_set(ipmi_oem_rsp_t *rsp)
-{
-	int ret;
-	ipmi_oem_req_t req;
-
-	if (rsp == NULL) {
-		printk(BIOS_ERR, "%s failed, null pointer parameter\n",
-			 __func__);
-		return 0;
-	}
-	/* IPMI OEM get bios boot order command to check if the valid bit and
-	   the CMOS clear bit are both set from the response BootMode byte. */
-	ret = ipmi_kcs_message(BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0,
-			IPMI_OEM_GET_BIOS_BOOT_ORDER,
-			(const unsigned char *) &req, sizeof(ipmi_oem_req_t),
-			(unsigned char *) rsp, sizeof(ipmi_oem_rsp_t));
-
-	if (ret < sizeof(struct ipmi_rsp) || rsp->CompletionCode) {
-		printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n",
-		__func__, ret, rsp->CompletionCode);
-		return 0;
-	}
-
-	if (GET_VALID_BIT(rsp->Data.BootMode) && GET_CMOS_BIT(rsp->Data.BootMode)) {
-		printk(BIOS_INFO, "IPMI CMOS clear requested\n");
-		return 1;
-	}
-
-	printk(BIOS_DEBUG, "IPMI CMOS clear is not set\n");
-	return 0;
-}
-
-void clear_ipmi_flags(ipmi_oem_rsp_t *rsp_get)
-{
-	int ret;
-	ipmi_oem_req_t req;
-	struct ipmi_rsp rsp;
-
-	if (rsp_get == NULL) {
-		printk(BIOS_ERR, "%s failed, null pointer parameter\n",
-			__func__);
-		return;
-	}
-
-	req = rsp_get->Data;
-	CLEAR_CMOS_AND_VALID_BIT(req.BootMode);
-	ret = ipmi_kcs_message(BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0,
-			IPMI_OEM_SET_BIOS_BOOT_ORDER,
-			(const unsigned char *) &req, sizeof(ipmi_oem_req_t),
-			(unsigned char *) &rsp, sizeof(rsp));
-
-	if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) {
-		printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n",
-			__func__, ret, rsp.completion_code);
-		return;
-	}
-
-	printk(BIOS_INFO, "clear IPMI flags done\n");
-}
diff --git a/src/mainboard/ocp/monolake/ipmi.h b/src/mainboard/ocp/monolake/ipmi.h
deleted file mode 100644
index 04649111c2..0000000000
--- a/src/mainboard/ocp/monolake/ipmi.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2019 Wiwynn Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef MONOLAKE_IPMI_H
-#define MONOLAKE_IPMI_H
-#include <types.h>
-
-#define IPMI_NETFN_OEM 0x30
-#define IPMI_OEM_SET_BIOS_BOOT_ORDER 0x52
-#define IPMI_OEM_GET_BIOS_BOOT_ORDER 0x53
-#define GET_CMOS_BIT(x) ((x) & (1 << 1))
-#define GET_VALID_BIT(x) ((x) & (1 << 7))
-#define CLEAR_CMOS_AND_VALID_BIT(x) ((x) &= 0x7d)
-#define BMC_KCS_BASE 0xca2
-typedef struct {
-	u8 BootMode; /* Bit 1:CMOS clear, bit 7:valid bit. */
-	u8 Boot0000;
-	u8 Boot0001;
-	u8 Boot0002;
-	u8 Boot0003;
-	u8 Boot0004;
-} __packed ipmi_oem_req_t;
-
-typedef struct {
-	u16 KcsRsp;
-	u8 CompletionCode;
-	ipmi_oem_req_t Data;
-} __packed ipmi_oem_rsp_t;
-
-/*
- * IPMI get response to check if valid and CMOS clear bit
- * are both set and store the IPMI response data to the parameter.
- */
-int is_ipmi_clear_cmos_set(ipmi_oem_rsp_t *rsp);
-/*
- * Clear valid bit and CMOS clear bit from the parameter
- * and set it back via IPMI.
- */
-void clear_ipmi_flags(ipmi_oem_rsp_t *rsp);
-
-#endif
diff --git a/src/mainboard/ocp/monolake/irqroute.c b/src/mainboard/ocp/monolake/irqroute.c
deleted file mode 100644
index f91cf0d5b3..0000000000
--- a/src/mainboard/ocp/monolake/irqroute.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "irqroute.h"
-
-DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/ocp/monolake/irqroute.h b/src/mainboard/ocp/monolake/irqroute.h
deleted file mode 100644
index c3911be75b..0000000000
--- a/src/mainboard/ocp/monolake/irqroute.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- * Copyright (C) 2015-2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef IRQROUTE_H
-#define IRQROUTE_H
-
-#include <soc/irq.h>
-#include <soc/pci_devs.h>
-
-#define PCI_DEV_PIRQ_ROUTES \
-	PCI_DEV_PIRQ_ROUTE(XHCI_DEV,  A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(ME_DEV,    A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(GBE_DEV,   A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(EHCI2_DEV, A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(HDA_DEV,   A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(PCIE_DEV,  A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(EHCI1_DEV, A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(SATA_DEV,  A, B, C, D)
-
-/*
- * Route each PIRQ[A-H] to a PIC IRQ[0-15]
- * Reserved: 0, 1, 2, 8, 13
- * ACPI/SCI: 9
- */
-#define PIRQ_PIC_ROUTES \
-	PIRQ_PIC(A,  5), \
-	PIRQ_PIC(B,  6), \
-	PIRQ_PIC(C,  7), \
-	PIRQ_PIC(D, 10), \
-	PIRQ_PIC(E, 11), \
-	PIRQ_PIC(F, 12), \
-	PIRQ_PIC(G, 14), \
-	PIRQ_PIC(H, 15)
-
-#endif /* IRQROUTE_H */
diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c
deleted file mode 100644
index dffd19f0f0..0000000000
--- a/src/mainboard/ocp/monolake/mainboard.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <pc80/mc146818rtc.h>
-#include <cf9_reset.h>
-#include <smbios.h>
-#include <string.h>
-#include <drivers/vpd/vpd.h>
-#include <console/console.h>
-#include <drivers/ipmi/ipmi_ops.h>
-#include "ipmi.h"
-/* VPD variable for enabling/disabling FRB2 timer. */
-#define FRB2_TIMER "FRB2_TIMER"
-/* VPD variable for setting FRB2 timer countdown value. */
-#define FRB2_COUNTDOWN "FRB2_COUNTDOWN"
-#define VPD_LEN 10
-/* Default countdown is 15 minutes. */
-#define DEFAULT_COUNTDOWN 9000
-
-static void init_frb2_wdt(void)
-{
-
-	char val[VPD_LEN];
-	/* Enable FRB2 timer by default. */
-	u8 enable = 1;
-	uint16_t countdown;
-
-	if (vpd_get_bool(FRB2_TIMER, VPD_RW, &enable)) {
-		if (!enable) {
-			printk(BIOS_DEBUG, "Disable FRB2 timer\n");
-			ipmi_stop_bmc_wdt(BMC_KCS_BASE);
-		}
-	}
-	if (enable) {
-		if (vpd_gets(FRB2_COUNTDOWN, val, VPD_LEN, VPD_RW)) {
-			countdown = (uint16_t)atol(val);
-			printk(BIOS_DEBUG, "FRB2 timer countdown set to: %d\n",
-				countdown);
-		} else {
-			printk(BIOS_DEBUG, "FRB2 timer use default value: %d\n",
-				DEFAULT_COUNTDOWN);
-			countdown = DEFAULT_COUNTDOWN;
-		}
-		ipmi_init_and_start_bmc_wdt(BMC_KCS_BASE, countdown,
-			TIMEOUT_HARD_RESET);
-	}
-}
-
-/*
- * mainboard_enable is executed as first thing after enumerate_buses().
- * This is the earliest point to add customization.
- */
-static void mainboard_enable(struct device *dev)
-{
-	ipmi_oem_rsp_t rsp;
-
-	init_frb2_wdt();
-	if (is_ipmi_clear_cmos_set(&rsp)) {
-		/* TODO: Should also try to restore CMOS to cmos.default
-		 * if USE_OPTION_TABLE is set */
-		cmos_init(1);
-		clear_ipmi_flags(&rsp);
-		system_reset();
-	}
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
-
-void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t)
-{
-
-	char locator[64] = {0};
-
-	snprintf(locator, sizeof(locator), "DIMM_%c%u", 'A' + dimm->channel_num,
-		 dimm->dimm_num);
-	t->device_locator = smbios_add_string(t->eos, locator);
-
-	snprintf(locator, sizeof(locator), "_Node0_Channel%d_Dimm%d", dimm->channel_num,
-		 dimm->dimm_num);
-	t->bank_locator = smbios_add_string(t->eos, locator);
-}
diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c
deleted file mode 100644
index ef41b7720e..0000000000
--- a/src/mainboard/ocp/monolake/romstage.c
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corp.
- * Copyright (C) 2019 Wiwynn Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stddef.h>
-#include <soc/romstage.h>
-#include <drivers/intel/fsp1_0/fsp_util.h>
-#include <drivers/vpd/vpd.h>
-#include <cpu/x86/msr.h>
-#include <cf9_reset.h>
-#include <console/console.h>
-#include <device/pci_ops.h>
-#include <soc/pci_devs.h>
-#include <soc/lpc.h>
-#include <soc/gpio.h>
-
-
-/* Define the strings for UPD variables that could be customized */
-#define FSP_VAR_HYPERTHREADING "HyperThreading"
-
-static const struct gpio_config gpio_tables[] = {
-	/* PU_BMBUSY_N */
-	{0, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* SKU_BDE_ID1 */
-	{1, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* FM_BDXDE_ERR0_LVT3_N */
-	{2, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* FM_BDXDE_ERR1_LVT3_N */
-	{3, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* FM_CPU2PCH_THROT_LVT3 */
-	{4, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* FM_BDXDE_CATERR_LVT3_N */
-	{5, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* SKU_BDE_ID2 */
-	{6, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* REV_BDE_ID0 */
-	{7, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* RQ_BMC_PCH_NMI_NOA1_CLK */
-	{8, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* FM_USB_OC_5_N */
-	{9, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* FM_USB_OC_6_N */
-	{10, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* PU_SMBALERT_N */
-	{11, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* RQ_IBMC_PCH_SMI_LPC_N */
-	{12, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* NC */
-	{13, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* FM_LVC3_RISER1_ID4_N_PU */
-	{14, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* PD_P1V2_VDDQ_SEL_N */
-	{15, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* FM_CPU_THROTTLE_N */
-	{16, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0},
-	/* SKU_BDE_ID0 */
-	{17, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* FM_SRC1CLKRQB */
-	{18, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* RST_PCIE_PCH_N */
-	{19, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* SMI_BMC_N_R */
-	{20, GPIO_MODE_NATIVE, 0, 0, 0, 0},
-	/* M_SATA0GP */
-	{21, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* SGPIO_SATA_CLOCK_R */
-	{22, GPIO_MODE_NATIVE, 0, 0, 0, 0},
-	/* TP */
-	{23, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* FAST_THROTTLE_N_R */
-	{24, GPIO_MODE_NATIVE, 0, 0, 0, 0},
-	/* BMC_READY_N */
-	{25, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* TP */
-	{26, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* FM_CPLD */
-	{27, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* FM_BDXDE_ME_DRIVE_N */
-	{28, GPIO_MODE_NATIVE, 0, 0, 0, 0},
-	/* H_BDXDE_PROCHOT_DISABLE */
-	{29, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0},
-	/* SUSPWRDNACK */
-	{30, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* SMB_INA230_ALRT_N */
-	{31, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* TP */
-	{32, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* PD_DMI_RX_TERMINATION */
-	{33, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0},
-	/* NC */
-	{34, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* NMI_BDE_R */
-	{35, GPIO_MODE_NATIVE, 0, 0, 0, 0},
-	/* FM_BIOS_ADV_FUNCTIONS */
-	{36, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* FM_ADR_TRIGGER_N */
-	{37, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* SGPIO_SATA_LOAD_R */
-	{38, GPIO_MODE_NATIVE, 0, 0, 0, 0},
-	/* SGPIO_SATA_DATAOUT0_R */
-	{39, GPIO_MODE_NATIVE, 0, 0, 0, 0},
-	/* FM_USB_OC_1_N */
-	{40, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* FM_USB_OC_2_N */
-	{41, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* FM_USB_OC_3_N */
-	{42, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* FM_USB_OC_4_N */
-	{43, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* TP */
-	{44, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* TP */
-	{45, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* FM_BIOS_POST_CMPLT_N */
-	{46, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0},
-	/* NC */
-	{47, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* PU_SGPIO_SATA_DATAOUT1 */
-	{48, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* FM_XDP_PCH_OBSDATA */
-	{49, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* PU_GSXCLK */
-	{50, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* PU_GSXDOUT */
-	{51, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* PD_CPUSV */
-	{52, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* PD_GSXDIN */
-	{53, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* PU_GSXSREST_N */
-	{54, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* PU_BIOS_RCVR_BOOT_J2 */
-	{55, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* NC */
-	{56, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* PU_ME_RCVR_N */
-	{57, GPIO_MODE_NATIVE, 0, 0, 0, 0},
-	/* SMB_SML1_3V3SB_CLK	 */
-	{58, GPIO_MODE_NATIVE, 0, 0, 0, 0},
-	/* FM_USB_OC_0_N */
-	{59, GPIO_MODE_NATIVE, 0, 0, 0, 0},
-	/* SMB_SML0_3V3SB_ALERT */
-	{60, GPIO_MODE_NATIVE, 0, 0, 0, 0},
-	/* SLP_SUS_STAT_N */
-	{61, GPIO_MODE_NATIVE, 0, 0, 0, 0},
-	/* CLK_CPLD_SUSCLK_R */
-	{62, GPIO_MODE_NATIVE, 0, 0, 0, 0},
-	/* NC */
-	{63, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* NC */
-	{64, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* NC */
-	{65, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* NC */
-	{66, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* NC */
-	{67, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* REV_BDE_ID1 */
-	{68, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* TPM_PRSNT_N */
-	{69, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* NC */
-	{70, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* NC */
-	{71, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* PU_BATLOW_N */
-	{72, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* NC */
-	{73, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
-	/* PCHHOT_CPU_N */
-	{74, GPIO_MODE_NATIVE, 0, 0, 0, 0},
-	/* SMB_SML1_3V3SB_DAT */
-	{75, GPIO_MODE_NATIVE, 0, 0, 0, 0},
-	{0xff, GPIO_LIST_END, 0, 0, 0, 0},
-};
-
-/**
- * /brief mainboard call for setup that needs to be done before fsp init
- *
- */
-void early_mainboard_romstage_entry(void)
-{
-	/*
-	 * Sometimes the system boots in an invalid state, where random values
-	 * have been written to MSRs and then the MSRs are locked.
-	 * Seems to always happen on warm reset.
-	 *
-	 * Power cycling or a board_reset() isn't sufficient in this case, so
-	 * issue a full_reset() to "fix" this issue.
-	 */
-	msr_t msr = rdmsr(IA32_FEATURE_CONTROL);
-	if (msr.lo & 1) {
-		console_init();
-		printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n");
-		full_reset();
-	}
-}
-
-/**
- * /brief mainboard call for setup that needs to be done after fsp init
- *
- */
-void late_mainboard_romstage_entry(void)
-{
-	// IPMI through BIC
-	pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC,
-			   0x0c0ca1);
-
-	// Initialize GPIOs
-	init_gpios(gpio_tables);
-}
-
-/*
- * This function sets up global variable to store VPD binary blob info,
- * and use settings in the binary blob to configure UPD.
- */
-static void board_configure_upd(UPD_DATA_REGION *UpdData)
-{
-	u8 val;
-
-	if (vpd_get_bool(FSP_VAR_HYPERTHREADING, VPD_RW, &val))
-		UpdData->HyperThreading = val;
-}
-
-/**
- * /brief customize fsp parameters, use data stored in VPD binary blob
- * to configure FSP UPD variables.
- */
-void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
-{
-	UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;
-
-	if (CONFIG(VPD))
-		board_configure_upd(UpdData);
-}
diff --git a/src/mainboard/ocp/monolake/vboot-ro.fmd b/src/mainboard/ocp/monolake/vboot-ro.fmd
deleted file mode 100644
index 44be3370ce..0000000000
--- a/src/mainboard/ocp/monolake/vboot-ro.fmd
+++ /dev/null
@@ -1,22 +0,0 @@
-FLASH 16M {
-	SI_ALL@0x0 0x800000 {
-		SI_DESC@0x0 0x1000
-		SI_ME@0x1000 0x7ff000
-	}
-	SI_BIOS@0x800000 0x800000 {
-		MISC_RW@0x0 0x20000 {
-			RW_MRC_CACHE@0x0 0x10000
-			RW_VPD(PRESERVE)@0x010000 0x4000
-		}
-		WP_RO@0x020000 0x7e0000 {
-			RO_VPD(PRESERVE)@0x0 0x4000
-			RO_SECTION@0x4000 0x7dc000 {
-				FMAP@0x0 0x800
-				RO_FRID@0x800 0x40
-				RO_FRID_PAD@0x840 0x7c0
-				GBB@0x1000 0x4000
-				COREBOOT(CBFS)@0x5000 0x7d7000
-			}
-		}
-	}
-}
diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig
deleted file mode 100644
index ef0fe88082..0000000000
--- a/src/mainboard/ocp/wedge100s/Kconfig
+++ /dev/null
@@ -1,61 +0,0 @@
-if BOARD_OCP_WEDGE100S
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select SOC_INTEL_FSP_BROADWELL_DE
-	select BOARD_ROMSIZE_KB_16384
-	select HAVE_ACPI_TABLES
-	select HAVE_OPTION_TABLE
-	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
-	select SERIRQ_CONTINUOUS_MODE
-	select FSP_EHCI1_ENABLE
-	select MRC_CACHE_FMAP
-	select ENABLE_FSP_FAST_BOOT
-	select MAINBOARD_HAS_LPC_TPM
-	select MAINBOARD_HAS_TPM1
-	select DRIVERS_UART_8250IO
-	select SUPERIO_ITE_IT8528E
-	select IPMI_KCS
-
-config VBOOT
-	select VBOOT_VBNV_CMOS
-	select VBOOT_NO_BOARD_SUPPORT
-	select GBB_FLAG_DISABLE_LID_SHUTDOWN
-	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
-	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
-	select GBB_FLAG_DISABLE_FWMP
-
-config MAINBOARD_DIR
-	string
-	default "ocp/wedge100s"
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Wedge 100S"
-
-config IRQ_SLOT_COUNT
-	int
-	default 18
-
-config CBFS_SIZE
-	hex
-	default 0x006fa000 if VBOOT
-	default 0x00200000
-
-config VIRTUAL_ROM_SIZE
-	hex
-	default 0x1000000
-
-config FSP_PACKAGE_DEFAULT
-	bool "Configure defaults for the Intel FSP package"
-	default n
-
-config FMDFILE
-	string
-	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-ro.fmd" if VBOOT
-	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
-
-config INTEGRATED_UART
-	def_bool n
-
-endif # BOARD_OCP_WEDGE100S
diff --git a/src/mainboard/ocp/wedge100s/Kconfig.name b/src/mainboard/ocp/wedge100s/Kconfig.name
deleted file mode 100644
index 2bfc19d61b..0000000000
--- a/src/mainboard/ocp/wedge100s/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_OCP_WEDGE100S
-	bool "Wedge 100S"
diff --git a/src/mainboard/ocp/wedge100s/Makefile.inc b/src/mainboard/ocp/wedge100s/Makefile.inc
deleted file mode 100644
index 1606476d80..0000000000
--- a/src/mainboard/ocp/wedge100s/Makefile.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2012 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-ramstage-y += irqroute.c
diff --git a/src/mainboard/ocp/wedge100s/acpi/mainboard.asl b/src/mainboard/ocp/wedge100s/acpi/mainboard.asl
deleted file mode 100644
index 62944ef353..0000000000
--- a/src/mainboard/ocp/wedge100s/acpi/mainboard.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Device (PWRB)
-{
-	Name(_HID, EisaId("PNP0C0C"))
-}
diff --git a/src/mainboard/ocp/wedge100s/acpi/platform.asl b/src/mainboard/ocp/wedge100s/acpi/platform.asl
deleted file mode 100644
index 7ffae2e6e0..0000000000
--- a/src/mainboard/ocp/wedge100s/acpi/platform.asl
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* The APM port can be used for generating software SMIs */
-
-OperationRegion (APMP, SystemIO, 0xb2, 2)
-Field (APMP, ByteAcc, NoLock, Preserve)
-{
-	APMC, 8,	// APM command
-	APMS, 8		// APM status
-}
-
-/* Port 80 POST */
-
-OperationRegion (POST, SystemIO, 0x80, 1)
-Field (POST, ByteAcc, Lock, Preserve)
-{
-	DBG0, 8
-}
-
-Name(\APC1, Zero) // IIO IOAPIC
-
-Name(\PICM, Zero) // IOAPIC/8259
-
-Method(_PIC, 1)
-{
-	Store(Arg0, PICM)
-}
-
-/* The _PTS method (Prepare To Sleep) is called before the OS is
- * entering a sleep state. The sleep state number is passed in Arg0
- */
-
-Method(_PTS,1)
-{
-}
-
-/* The _WAK method is called on system wakeup */
-
-Method(_WAK,1)
-{
-	Return(Package(){0,0})
-}
diff --git a/src/mainboard/ocp/wedge100s/acpi_tables.c b/src/mainboard/ocp/wedge100s/acpi_tables.c
deleted file mode 100644
index 0197def7a7..0000000000
--- a/src/mainboard/ocp/wedge100s/acpi_tables.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- * Copyright (C) 2015-2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/ioapic.h>
-#include <soc/acpi.h>
-#include <soc/iomap.h>
-
-extern const unsigned char AmlCode[];
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	u32 i;
-
-	current = acpi_create_madt_lapics(current);
-
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 8,
-		IOXAPIC1_BASE_ADDRESS, 0);
-	set_ioapic_id((u8 *)IOXAPIC1_BASE_ADDRESS, 8);
-
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 9,
-		IOXAPIC2_BASE_ADDRESS, 24);
-	set_ioapic_id((u8 *)IOXAPIC2_BASE_ADDRESS, 9);
-
-	current = acpi_madt_irq_overrides(current);
-
-	for (i = 0; i < 16; i++)
-		current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, i, 0xD, 1);
-
-	return current;
-}
diff --git a/src/mainboard/ocp/wedge100s/board.fmd b/src/mainboard/ocp/wedge100s/board.fmd
deleted file mode 100644
index 8e440810e6..0000000000
--- a/src/mainboard/ocp/wedge100s/board.fmd
+++ /dev/null
@@ -1,27 +0,0 @@
-FLASH@0xff000000 0x1000000 {
-	SI_ALL@0x0 0x800000 {
-		SI_DESC@0x0 0x1000
-		SI_ME@0x1000 0x7ff000
-	}
-	SI_BIOS@0x800000 0x800000 {
-		FMAP@0x0 0x1000
-		RW_MISC@0x1000 0xe000 {
-			RW_ELOG@0x0 0x4000
-			RW_VPD@0x4000 0x2000
-			RW_MISC_UNUSED@0x6000 0x5000
-			RW_NVRAM@0xc000 0x2000
-#			UNIFIED_MRC_CACHE@0x10000 0x20000 {
-#				RECOVERY_MRC_CACHE@0x0 0x10000
-#				RW_MRC_CACHE@0x10000 0x10000
-#			}
-		}
-		UNUSED@0xf000 0x1000 {
-			# This only exists to satisfy tools that
-			# specifically look for RO_VPD.
-			RO_VPD@0x0 0x1000
-		}
-		RW_MRC_CACHE@0x10000 0x10000
-		CONSOLE@0x20000 0x10000
-		COREBOOT(CBFS)@0x30000 0x7d0000
-	}
-}
diff --git a/src/mainboard/ocp/wedge100s/board_info.txt b/src/mainboard/ocp/wedge100s/board_info.txt
deleted file mode 100644
index e8c178fbe0..0000000000
--- a/src/mainboard/ocp/wedge100s/board_info.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-Board name: Wedge 100S
-Category: server
-ROM protocol: SPI
-ROM socketed: yes
-Release year: 2017
diff --git a/src/mainboard/ocp/wedge100s/cmos.layout b/src/mainboard/ocp/wedge100s/cmos.layout
deleted file mode 100644
index 3aaa56b569..0000000000
--- a/src/mainboard/ocp/wedge100s/cmos.layout
+++ /dev/null
@@ -1,120 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-# -----------------------------------------------------------------
-entries
-
-#start-bit length  config config-ID    name
-#0            8       r       0        seconds
-#8            8       r       0        alarm_seconds
-#16           8       r       0        minutes
-#24           8       r       0        alarm_minutes
-#32           8       r       0        hours
-#40           8       r       0        alarm_hours
-#48           8       r       0        day_of_week
-#56           8       r       0        day_of_month
-#64           8       r       0        month
-#72           8       r       0        year
-# -----------------------------------------------------------------
-# Status Register A
-#80           4       r       0        rate_select
-#84           3       r       0        REF_Clock
-#87           1       r       0        UIP
-# -----------------------------------------------------------------
-# Status Register B
-#88           1       r       0        auto_switch_DST
-#89           1       r       0        24_hour_mode
-#90           1       r       0        binary_values_enable
-#91           1       r       0        square-wave_out_enable
-#92           1       r       0        update_finished_enable
-#93           1       r       0        alarm_interrupt_enable
-#94           1       r       0        periodic_interrupt_enable
-#95           1       r       0        disable_clock_updates
-# -----------------------------------------------------------------
-# Status Register C
-#96           4       r       0        status_c_rsvd
-#100          1       r       0        uf_flag
-#101          1       r       0        af_flag
-#102          1       r       0        pf_flag
-#103          1       r       0        irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104          7       r       0        status_d_rsvd
-#111          1       r       0        valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112          8       r       0        diag_rsvd1
-
-# -----------------------------------------------------------------
-0          120       r       0        reserved_memory
-#120        264       r       0        unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#390          2       r       0        unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-#392          3       r       0        unused
-395          4       e       6        debug_level
-#399          1       r       0        unused
-
-# coreboot config options: cpu
-400          1       e       2        hyper_threading
-#401          7       r       0        unused
-
-# coreboot config options: southbridge
-408          1       e       1        nmi
-409          2       e       7        power_on_after_fail
-#411          5       r       0        unused
-416          128      r      0        vbnv
-
-# MRC Scrambler Seed values
-896         32        r       0        mrc_scrambler_seed
-928         32        r       0        mrc_scrambler_seed_s3
-
-# coreboot config options: check sums
-984         16       h       0        check_sum
-#1000        24       r       0        amd_reserved
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     0     Emergency
-6     1     Alert
-6     2     Critical
-6     3     Error
-6     4     Warning
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-7     0     Disable
-7     1     Enable
-7     2     Keep
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 415 984
diff --git a/src/mainboard/ocp/wedge100s/devicetree.cb b/src/mainboard/ocp/wedge100s/devicetree.cb
deleted file mode 100644
index 3552a6db1b..0000000000
--- a/src/mainboard/ocp/wedge100s/devicetree.cb
+++ /dev/null
@@ -1,74 +0,0 @@
-chip soc/intel/fsp_broadwell_de
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-	device domain 0 on
-		device pci 00.0 on end # SoC router
-		device pci 01.0 on # PCIe x1
-			# Intel i210t
-		end
-		device pci 02.0 on # PCIe x1
-			# QuickData Technology
-		end
-		device pci 02.2 on # PCIe x1
-			# Intel X552 10 GbE SFP+
-		end
-		device pci 03.0 on end # PEG 16x
-		device pci 05.0 on end # Vtd
-		device pci 05.1 on end # IIO Hotplug
-		device pci 05.2 on end # IIO
-		device pci 05.4 on end # PIC
-		device pci 14.0 off end # xHCI Controller
-		device pci 1c.0 on # PCH PCIe Gen2 x4
-			# BCM56960 Switch ASIC
-		end
-		device pci 1d.0 on end # PCH EHCI Controller
-		device pci 1f.0 on # LPC
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-			chip superio/ite/it8528e
-				# COM1, routed to COM-e header
-				device pnp 6e.1 on
-					io 0x60 = 0x3f8
-					irq 0x70 = 4
-				end
-				# COM2, routed to COM-e header
-				device pnp 6e.2 on
-					io 0x60 = 0x2f8
-					irq 0x70 = 3
-				end
-				device pnp 6e.4 off end
-				device pnp 6e.5 off end
-				device pnp 6e.6 off end
-				device pnp 6e.a off end
-				device pnp 6e.f off end
-				device pnp 6e.10 off end
-				device pnp 6e.11 on
-					io 0x60 = 0x62
-					io 0x62 = 0x66
-					irq 0x70 = 1
-				end
-				device pnp 6e.12 on
-					io 0x60 = 0x68
-					io 0x62 = 0x6c
-					irq 0x70 = 1
-				end
-				device pnp 6e.13 off end
-				device pnp 6e.14 off end
-				device pnp 6e.17 off end
-				device pnp 6e.18 off end
-				device pnp 6e.19 off end
-			end	#superio/ite/it8528e
-			chip drivers/ipmi
-				device pnp ca2.0 on end		# IPMI KCS
-			end
-		end # LPC Bridge
-		device pci 1f.2 on end # SATA Controller
-		device pci 1f.3 on end # SMBus Controller
-		device pci 1f.5 off end # SATA Controller
-		device pci 1f.6 on # Thermal Management Controller
-			# DON'T DISABLE, CRASHES FSP MR2
-		end
-	end
-end
diff --git a/src/mainboard/ocp/wedge100s/dsdt.asl b/src/mainboard/ocp/wedge100s/dsdt.asl
deleted file mode 100644
index 1248703266..0000000000
--- a/src/mainboard/ocp/wedge100s/dsdt.asl
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2015-2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	0x02,		// DSDT revision: ACPI v2.0 and up
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x20110725	// OEM revision
-)
-{
-	#include "acpi/platform.asl"
-
-	Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 })
-	Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 })
-
-	Scope (\_SB)
-	{
-		Device (PCI0)
-		{
-			#include <acpi/southcluster.asl>
-			#include <acpi/pcie1.asl>
-		}
-
-		Name (PRUN, Package() {
-			Package() { 0x0008FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0008FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0008FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0008FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x0009FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0009FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0009FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0009FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x000AFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x000AFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x000AFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x000AFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x000BFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x000BFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x000BFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x000BFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x000CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x000CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x000CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x000CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x000DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x000DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x000DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x000DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x000EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x000EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x000EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x000EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x000FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x000FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x000FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x000FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x0010FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0010FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0010FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0010FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x0011FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0011FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0011FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0011FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x0012FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0012FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0012FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0012FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x0013FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0013FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0013FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0013FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x0014FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0014FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0014FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0014FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x0016FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0016FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0016FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0016FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x0017FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0017FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0017FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0017FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x0018FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0018FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0018FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0018FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x0019FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x0019FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x0019FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x0019FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x001CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x001CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x001CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x001CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x001DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x001DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x001DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x001DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x001EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x001EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x001EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x001EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-
-			Package() { 0x001FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
-			Package() { 0x001FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
-			Package() { 0x001FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
-			Package() { 0x001FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
-		})
-
-		Name (ARUN, Package() {
-			Package() { 0x0008FFFF, 0, 0, 16 },
-			Package() { 0x0008FFFF, 1, 0, 17 },
-			Package() { 0x0008FFFF, 2, 0, 18 },
-			Package() { 0x0008FFFF, 3, 0, 19 },
-
-			Package() { 0x0009FFFF, 0, 0, 16 },
-			Package() { 0x0009FFFF, 1, 0, 17 },
-			Package() { 0x0009FFFF, 2, 0, 18 },
-			Package() { 0x0009FFFF, 3, 0, 19 },
-
-			Package() { 0x000AFFFF, 0, 0, 16 },
-			Package() { 0x000AFFFF, 1, 0, 17 },
-			Package() { 0x000AFFFF, 2, 0, 18 },
-			Package() { 0x000AFFFF, 3, 0, 19 },
-
-			Package() { 0x000BFFFF, 0, 0, 16 },
-			Package() { 0x000BFFFF, 1, 0, 17 },
-			Package() { 0x000BFFFF, 2, 0, 18 },
-			Package() { 0x000BFFFF, 3, 0, 19 },
-
-			Package() { 0x000CFFFF, 0, 0, 16 },
-			Package() { 0x000CFFFF, 1, 0, 17 },
-			Package() { 0x000CFFFF, 2, 0, 18 },
-			Package() { 0x000CFFFF, 3, 0, 19 },
-
-			Package() { 0x000DFFFF, 0, 0, 16 },
-			Package() { 0x000DFFFF, 1, 0, 17 },
-			Package() { 0x000DFFFF, 2, 0, 18 },
-			Package() { 0x000DFFFF, 3, 0, 19 },
-
-			Package() { 0x000EFFFF, 0, 0, 16 },
-			Package() { 0x000EFFFF, 1, 0, 17 },
-			Package() { 0x000EFFFF, 2, 0, 18 },
-			Package() { 0x000EFFFF, 3, 0, 19 },
-
-			Package() { 0x000FFFFF, 0, 0, 16 },
-			Package() { 0x000FFFFF, 1, 0, 17 },
-			Package() { 0x000FFFFF, 2, 0, 18 },
-			Package() { 0x000FFFFF, 3, 0, 19 },
-
-			Package() { 0x0010FFFF, 0, 0, 16 },
-			Package() { 0x0010FFFF, 1, 0, 17 },
-			Package() { 0x0010FFFF, 2, 0, 18 },
-			Package() { 0x0010FFFF, 3, 0, 19 },
-
-			Package() { 0x0011FFFF, 0, 0, 16 },
-			Package() { 0x0011FFFF, 1, 0, 17 },
-			Package() { 0x0011FFFF, 2, 0, 18 },
-			Package() { 0x0011FFFF, 3, 0, 19 },
-
-			Package() { 0x0012FFFF, 0, 0, 16 },
-			Package() { 0x0012FFFF, 1, 0, 17 },
-			Package() { 0x0012FFFF, 2, 0, 18 },
-			Package() { 0x0012FFFF, 3, 0, 19 },
-
-			Package() { 0x0013FFFF, 0, 0, 16 },
-			Package() { 0x0013FFFF, 1, 0, 17 },
-			Package() { 0x0013FFFF, 2, 0, 18 },
-			Package() { 0x0013FFFF, 3, 0, 19 },
-
-			Package() { 0x0014FFFF, 0, 0, 16 },
-			Package() { 0x0014FFFF, 1, 0, 17 },
-			Package() { 0x0014FFFF, 2, 0, 18 },
-			Package() { 0x0014FFFF, 3, 0, 19 },
-
-			Package() { 0x0016FFFF, 0, 0, 16 },
-			Package() { 0x0016FFFF, 1, 0, 17 },
-			Package() { 0x0016FFFF, 2, 0, 18 },
-			Package() { 0x0016FFFF, 3, 0, 19 },
-
-			Package() { 0x0017FFFF, 0, 0, 16 },
-			Package() { 0x0017FFFF, 1, 0, 17 },
-			Package() { 0x0017FFFF, 2, 0, 18 },
-			Package() { 0x0017FFFF, 3, 0, 19 },
-
-			Package() { 0x0018FFFF, 0, 0, 16 },
-			Package() { 0x0018FFFF, 1, 0, 17 },
-			Package() { 0x0018FFFF, 2, 0, 18 },
-			Package() { 0x0018FFFF, 3, 0, 19 },
-
-			Package() { 0x0019FFFF, 0, 0, 16 },
-			Package() { 0x0019FFFF, 1, 0, 17 },
-			Package() { 0x0019FFFF, 2, 0, 18 },
-			Package() { 0x0019FFFF, 3, 0, 19 },
-
-			Package() { 0x001CFFFF, 0, 0, 16 },
-			Package() { 0x001CFFFF, 1, 0, 17 },
-			Package() { 0x001CFFFF, 2, 0, 18 },
-			Package() { 0x001CFFFF, 3, 0, 19 },
-
-			Package() { 0x001DFFFF, 0, 0, 16 },
-			Package() { 0x001DFFFF, 1, 0, 17 },
-			Package() { 0x001DFFFF, 2, 0, 18 },
-			Package() { 0x001DFFFF, 3, 0, 19 },
-
-			Package() { 0x001EFFFF, 0, 0, 16 },
-			Package() { 0x001EFFFF, 1, 0, 17 },
-			Package() { 0x001EFFFF, 2, 0, 18 },
-			Package() { 0x001EFFFF, 3, 0, 19 },
-
-			Package() { 0x001FFFFF, 0, 0, 16 },
-			Package() { 0x001FFFFF, 1, 0, 17 },
-			Package() { 0x001FFFFF, 2, 0, 18 },
-			Package() { 0x001FFFFF, 3, 0, 19 },
-		})
-
-		Device (UNC0)
-		{
-			Name (_HID, EisaId ("PNP0A03"))
-			Name (_UID, 0x3F)
-			Method (_BBN, 0, NotSerialized)
-			{
-				Return (0xff)
-			}
-
-			Name (_ADR, 0x00)
-			Method (_STA, 0, NotSerialized)
-			{
-				Return (0xf)
-			}
-
-			Name (_CRS, ResourceTemplate ()
-			{
-				WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
-					0x0000,             // Granularity
-					0x00FF,             // Range Minimum
-					0x00FF,             // Range Maximum
-					0x0000,             // Translation Offset
-					0x0001,             // Length
-					,, )
-			})
-
-			Method (_PRT, 0, NotSerialized)
-			{
-				If (LEqual (PICM, Zero))
-				{
-					Return (PRUN)
-				}
-
-				Return (ARUN)
-			}
-		}
-	}
-
-	#include "acpi/mainboard.asl"
-}
diff --git a/src/mainboard/ocp/wedge100s/fadt.c b/src/mainboard/ocp/wedge100s/fadt.c
deleted file mode 100644
index 5af6056b49..0000000000
--- a/src/mainboard/ocp/wedge100s/fadt.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/acpi.h>
-
-void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
-{
-	acpi_header_t *header = &(fadt->header);
-
-	acpi_fill_in_fadt(fadt, facs, dsdt);
-
-	/* Platform specific customizations go here */
-
-	header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
-}
diff --git a/src/mainboard/ocp/wedge100s/irqroute.c b/src/mainboard/ocp/wedge100s/irqroute.c
deleted file mode 100644
index f91cf0d5b3..0000000000
--- a/src/mainboard/ocp/wedge100s/irqroute.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "irqroute.h"
-
-DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/ocp/wedge100s/irqroute.h b/src/mainboard/ocp/wedge100s/irqroute.h
deleted file mode 100644
index c3911be75b..0000000000
--- a/src/mainboard/ocp/wedge100s/irqroute.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- * Copyright (C) 2015-2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef IRQROUTE_H
-#define IRQROUTE_H
-
-#include <soc/irq.h>
-#include <soc/pci_devs.h>
-
-#define PCI_DEV_PIRQ_ROUTES \
-	PCI_DEV_PIRQ_ROUTE(XHCI_DEV,  A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(ME_DEV,    A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(GBE_DEV,   A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(EHCI2_DEV, A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(HDA_DEV,   A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(PCIE_DEV,  A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(EHCI1_DEV, A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(SATA_DEV,  A, B, C, D)
-
-/*
- * Route each PIRQ[A-H] to a PIC IRQ[0-15]
- * Reserved: 0, 1, 2, 8, 13
- * ACPI/SCI: 9
- */
-#define PIRQ_PIC_ROUTES \
-	PIRQ_PIC(A,  5), \
-	PIRQ_PIC(B,  6), \
-	PIRQ_PIC(C,  7), \
-	PIRQ_PIC(D, 10), \
-	PIRQ_PIC(E, 11), \
-	PIRQ_PIC(F, 12), \
-	PIRQ_PIC(G, 14), \
-	PIRQ_PIC(H, 15)
-
-#endif /* IRQROUTE_H */
diff --git a/src/mainboard/ocp/wedge100s/mainboard.c b/src/mainboard/ocp/wedge100s/mainboard.c
deleted file mode 100644
index 93c2a58f74..0000000000
--- a/src/mainboard/ocp/wedge100s/mainboard.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#if CONFIG(VGA_ROM_RUN)
-#include <x86emu/x86emu.h>
-#endif
-
-/*
- * mainboard_enable is executed as first thing after enumerate_buses().
- * This is the earliest point to add customization.
- */
-static void mainboard_enable(struct device *dev)
-{
-
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/ocp/wedge100s/romstage.c b/src/mainboard/ocp/wedge100s/romstage.c
deleted file mode 100644
index 108d7a1c4d..0000000000
--- a/src/mainboard/ocp/wedge100s/romstage.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stddef.h>
-#include <soc/romstage.h>
-#include <drivers/intel/fsp1_0/fsp_util.h>
-#include <cpu/x86/msr.h>
-#include <cf9_reset.h>
-#include <console/console.h>
-#include <device/pci_ops.h>
-#include <soc/pci_devs.h>
-#include <soc/lpc.h>
-#include <superio/ite/common/ite.h>
-
-#define SUPERIO_DEV 0x6e
-#define SERIAL_DEV PNP_DEV(SUPERIO_DEV, 1)
-
-/**
- * /brief mainboard call for setup that needs to be done before fsp init
- *
- */
-void early_mainboard_romstage_entry(void)
-{
-	/* Decode 0x6e/0x6f on LPC bus (actually 0x6c-0x6f) */
-	pci_write_config32(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_GEN1_DEC,
-			   (0 << 16) | ALIGN_DOWN(SUPERIO_DEV, 4) | 1);
-
-	/* Decode IPMI KCS */
-	pci_write_config32(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC,
-			   (0 << 16) | ALIGN_DOWN(0xca2, 4) | 1);
-
-	if (CONFIG(CONSOLE_SERIAL))
-		ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
-
-	/*
-	 * Sometimes the system boots in an invalid state, where random values
-	 * have been written to MSRs and then the MSRs are locked.
-	 * Seems to always happen on warm reset.
-	 *
-	 * Power cycling or a board_reset() isn't sufficient in this case, so
-	 * issue a full_reset() to "fix" this issue.
-	 *
-	 * It seems to be a deficiency in the reset logic, as other
-	 * FSP broadwell DE boards are not affected.
-	 */
-	msr_t msr = rdmsr(IA32_FEATURE_CONTROL);
-	if (msr.lo & 1) {
-		console_init();
-		printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n");
-		full_reset();
-	}
-}
-
-/**
- * /brief mainboard call for setup that needs to be done after fsp init
- *
- */
-void late_mainboard_romstage_entry(void)
-{
-
-}
-
-/**
- * /brief customize fsp parameters here if needed
- */
-void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
-{
-	UPD_DATA_REGION *fsp_upd_data = FspRtBuffer->Common.UpdDataRgnPtr;
-	if (CONFIG(FSP_USES_UPD)) {
-		/* The internal UART operates on 0x3f8/0x2f8.
-		 * As it's not wired up and conflicts with SuperIO decoding
-		 * the same range, make sure to disable it.
-		 */
-		fsp_upd_data->SerialPortControllerInit0 = 0;
-		fsp_upd_data->SerialPortControllerInit1 = 0;
-
-		/* coreboot will initialize UART.
-		 * No need for FSP to do it again.
-		 */
-		fsp_upd_data->SerialPortConfigure = 0;
-		fsp_upd_data->SerialPortBaudRate = 0;
-
-		/* Make FSP use serial IO */
-		if (CONFIG(CONSOLE_SERIAL))
-			fsp_upd_data->SerialPortType = 1;
-		else
-			fsp_upd_data->SerialPortType = 0;
-	}
-}
diff --git a/src/mainboard/ocp/wedge100s/vboot-ro.fmd b/src/mainboard/ocp/wedge100s/vboot-ro.fmd
deleted file mode 100644
index 1413bbff29..0000000000
--- a/src/mainboard/ocp/wedge100s/vboot-ro.fmd
+++ /dev/null
@@ -1,22 +0,0 @@
-FLASH 16M {
-	SI_ALL@0x0 0x800000 {
-		SI_DESC@0x0 0x1000
-		SI_ME@0x1000 0x7ff000
-	}
-	SI_BIOS@0x800000 0x800000 {
-		MISC_RW@0x0 0x20000 {
-			RW_MRC_CACHE@0x0 0x10000
-			RW_VPD(PRESERVE)@0x010000 0x4000
-		}
-		WP_RO@0x020000 0x7e0000 {
-			RO_VPD(PRESERVE)@0x0 0x4000
-			RO_SECTION@0x4000 0x7dc000 {
-				FMAP@0x0 0x800
-				RO_FRID@0x800 0x40
-				RO_FRID_PAD@0x840 0x7c0
-				GBB@0x1000 0xef000
-				COREBOOT(CBFS)@0xf0000 0x6ec000
-			}
-		}
-	}
-}