diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2020-11-10 15:55:31 +0100 |
---|---|---|
committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-28 13:39:39 +0000 |
commit | 7a36ca5a3af464bab21e61256e41c4c8eb220f7d (patch) | |
tree | bdd607596430ffce17d5191690a0e11e98745156 /src/mainboard/ocp | |
parent | 42a6f7e417f64a475f6e2b54ea59ee0a733a9c79 (diff) |
soc/intel/xeon_sp: Lock down IIO DFX Global registers
This is required for CbNT.
Change-Id: I565a95cd2e76cb1c648884be6d1954288f6e4804
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/ocp')
-rw-r--r-- | src/mainboard/ocp/deltalake/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index d51391da42..06448c38eb 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -63,6 +63,9 @@ chip soc/intel/xeon_sp/cpx device pci 05.0 on end # Intel SkyLake-E MM/Vt-d Configuration Registers device pci 05.2 on end # Intel SkyLake-E RAS device pci 05.4 on end # Intel SkyLake-E IOAPIC + device pci 07.0 on end + device pci 07.4 on end + device pci 07.7 on end device pci 08.0 on end # System peripheral: Intel SkyLake-E Ubox Registers device pci 08.1 on end # Performance counters: Intel SkyLake-E Ubox Registers device pci 08.2 on end # System peripheral: Intel SkyLake-E Ubox Registers |