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authorJulius Werner <jwerner@chromium.org>2019-03-05 16:53:33 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-03-08 08:33:24 +0000
commitcd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch)
tree8e89136e2da7cf54453ba8c112eda94415b56242 /src/mainboard/ocp/wedge100s
parentb3a8cc54dbaf833c590a56f912209a5632b71f49 (diff)
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/ocp/wedge100s')
-rw-r--r--src/mainboard/ocp/wedge100s/mainboard.c2
-rw-r--r--src/mainboard/ocp/wedge100s/romstage.c6
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/ocp/wedge100s/mainboard.c b/src/mainboard/ocp/wedge100s/mainboard.c
index f1a3a208ee..93c2a58f74 100644
--- a/src/mainboard/ocp/wedge100s/mainboard.c
+++ b/src/mainboard/ocp/wedge100s/mainboard.c
@@ -15,7 +15,7 @@
*/
#include <device/device.h>
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
#include <x86emu/x86emu.h>
#endif
diff --git a/src/mainboard/ocp/wedge100s/romstage.c b/src/mainboard/ocp/wedge100s/romstage.c
index b8da280e9b..7fdc981915 100644
--- a/src/mainboard/ocp/wedge100s/romstage.c
+++ b/src/mainboard/ocp/wedge100s/romstage.c
@@ -38,7 +38,7 @@ void early_mainboard_romstage_entry(void)
pci_write_config32(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_GEN1_DEC,
(0 << 16) | ALIGN_DOWN(SUPERIO_DEV, 4) | 1);
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
+ if (CONFIG(CONSOLE_SERIAL))
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -76,7 +76,7 @@ void late_mainboard_romstage_entry(void)
void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
{
UPD_DATA_REGION *fsp_upd_data = FspRtBuffer->Common.UpdDataRgnPtr;
- if (IS_ENABLED(CONFIG_FSP_USES_UPD)) {
+ if (CONFIG(FSP_USES_UPD)) {
/* The internal UART operates on 0x3f8/0x2f8.
* As it's not wired up and conflicts with SuperIO decoding
* the same range, make sure to disable it.
@@ -91,7 +91,7 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
fsp_upd_data->SerialPortBaudRate = 0;
/* Make FSP use serial IO */
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
+ if (CONFIG(CONSOLE_SERIAL))
fsp_upd_data->SerialPortType = 1;
else
fsp_upd_data->SerialPortType = 0;