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authorPatrick Rudolph <patrick.rudolph@9elements.com>2019-01-16 14:51:18 +0100
committerFelix Held <felix-coreboot@felixheld.de>2019-01-24 09:10:52 +0000
commit4c2ce72341c4e3baae27ec36706d00f8276c5ebe (patch)
treea19e3356c02ef4955f3fcc26e3c92db3e2578ca1 /src/mainboard/ocp/wedge100s/devicetree.cb
parent5449007425c23dd1b5aaeb64d6ab976893ffe023 (diff)
mb/ocp/wedge100s: Add SuperIO support
* Enable COM1, COM2, PMC1 and PMC2 TODO: Look at additional configuration and EC space. Tested on wedge100s. The serial works without CONFIG_CONSOLE_SERIAL. Change-Id: Id139bf243c7e7ac3e51a0ddb19d2396452341e29 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/ocp/wedge100s/devicetree.cb')
-rw-r--r--src/mainboard/ocp/wedge100s/devicetree.cb33
1 files changed, 33 insertions, 0 deletions
diff --git a/src/mainboard/ocp/wedge100s/devicetree.cb b/src/mainboard/ocp/wedge100s/devicetree.cb
index 3d66d0d361..bbea89e558 100644
--- a/src/mainboard/ocp/wedge100s/devicetree.cb
+++ b/src/mainboard/ocp/wedge100s/devicetree.cb
@@ -11,6 +11,39 @@ chip soc/intel/fsp_broadwell_de
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
+ chip superio/ite/it8528e
+ # COM1, routed to COM-e header
+ device pnp 6e.1 on
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ # COM2, routed to COM-e header
+ device pnp 6e.2 on
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 6e.4 off end
+ device pnp 6e.5 off end
+ device pnp 6e.6 off end
+ device pnp 6e.a off end
+ device pnp 6e.f off end
+ device pnp 6e.10 off end
+ device pnp 6e.11 on
+ io 0x60 = 0x62
+ io 0x62 = 0x66
+ irq 0x70 = 1
+ end
+ device pnp 6e.12 on
+ io 0x60 = 0x68
+ io 0x62 = 0x6c
+ irq 0x70 = 1
+ end
+ device pnp 6e.13 off end
+ device pnp 6e.14 off end
+ device pnp 6e.17 off end
+ device pnp 6e.18 off end
+ device pnp 6e.19 off end
+ end #superio/ite/it8528e
end # LPC Bridge
device pci 1f.2 on end # SATA Controller
device pci 1f.3 on end # SMBus Controller