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| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2020-03-09 14:07:28 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-04-15 14:05:55 +0000 |
| commit | 31fef3f6f8a417c80bdcbebfe99d05adbb197389 (patch) | |
| tree | b8d47e5b14aa6228cbdc45cf05baf9ad02a9e6e1 /src/mainboard/ocp/tiogapass | |
| parent | 6d2a51eb850e7d86da0f7c3269cae606a68cbd78 (diff) | |
mb/intel/jasperlake_rvp: Update JSLRVP USB configuration
Remove extra USB port entry because it came in from copy
patch from the previous board and configure USB over-current
pins as per JSLRVP.
Change-Id: If9df8e330d31ed81207dfdfa2ab96fd4d49f3f0c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39403
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/ocp/tiogapass')
0 files changed, 0 insertions, 0 deletions