diff options
author | Bryant Ou <Bryant.Ou.Q@gmail.com> | 2020-07-16 20:19:17 -0700 |
---|---|---|
committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-28 09:04:55 +0000 |
commit | 9ccd3114ffbbf0e1f0972169720fb86a6b6ad504 (patch) | |
tree | ce30c21ae667021557907e7bc4cab6e3581e29a8 /src/mainboard/ocp/deltalake/ramstage.c | |
parent | 4a6c0a368e96e393ef48606d6be30bbd9aee2d36 (diff) |
mb/ocp/deltalake: use common driver to configure GPIO
Use the common driver to configure the GPIOs on the Delta Lake
platform as done for Tioga Pass in commit 89d2aa0. The GPIO
settings are dumped by inteltool with original UEFI firmware,
then use intelp2m to generate header file.
TEST=Dump GPIO settings by Intel ITP and check if match gpio.h.
Change-Id: I8005d4caa2d87b6831099bfec3a40246224f3cb5
Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/ocp/deltalake/ramstage.c')
-rw-r--r-- | src/mainboard/ocp/deltalake/ramstage.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 4418ea4bab..17f33bd905 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -14,6 +14,7 @@ #include <device/pci_ops.h> #include <soc/util.h> #include <hob_iiouds.h> +#include <cpxsp_dl_gpio.h> #include "ipmi.h" @@ -222,6 +223,8 @@ static void mainboard_enable(struct device *dev) void mainboard_silicon_init_params(FSPS_UPD *params) { + /* configure Lewisburg PCH GPIO controller after FSP-M */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); } static void mainboard_final(void *chip_info) |