mb/ocp/deltalake: Add OCP Delta Lake mainboard

OCP Delta Lake server is a one socket server platform powered by
Intel Cooper Lake Scalable Processor.

The Delta Lake server is a blade of OCP Yosemite V3 multi-host
sled.

TESTED=Successfully booted on both YV3 config A Delta Lake server
and config C Delta Lake server. The coreboot payload is Linux kernel
plus u-root as initramfs. Below are the logs of ssh'ing into a
config C deltalake server:
jonzhang@devvm2573:~$ ssh yv3-cth
root@ip's password:
Last login: Mon Apr 20 21:56:51 2020 from
[root@dhcp-100-96-192-156 ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                52
On-line CPU(s) list:   0-51
...
[root@dhcp-100-96-192-156 ~]# cbmem
34 entries total:

   0:1st timestamp                                     28,621,996
  40:device configuration                              178,835,602 (150,213,605)
...
Total Time: 135,276,123,874,479,544
[root@dhcp-100-96-192-156 ~]# cat /proc/cmdline
root=UUID=f0fc52f2-e8b8-40f8-ac42-84c9f838394c ro crashkernel=auto selinux=0 console=ttyS1,57600n1 LANG=en_US.UTF-8 earlyprintk=serial,ttyS0,57600 earlyprintk=uart8250,io,0x2f8,57600n1 console=ttyS0,57600n1 loglevel=7 systemd.log_level=debug

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I0a5234d483e4ddea1cd37643b41f6aba65729c8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

1 files changed, 62 insertions, 0 deletions

diff --git a/src/mainboard/ocp/deltalake/bootblock.c b/src/mainboard/ocp/deltalake/bootblock.c
new file mode 100644
index 0000000000..8004170a5e
--- /dev/null
+++ b/src/mainboard/ocp/deltalake/bootblock.c
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <device/pnp_ops.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
+#include <soc/intel/common/block/lpc/lpc_def.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <superio/aspeed/ast2400/ast2400.h>
+#include <superio/aspeed/common/aspeed.h>
+
+#define ASPEED_SIO_PORT 0x2E
+
+static void enable_espi_lpc_io_windows(void)
+{
+	/*
+	 * Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports,
+	 * one is connected to debug header (SUART1) and another is used as SOL (SUART2).
+	 * For that end it is wired into BMC virtual port.
+	 */
+	uint16_t lpciod = (LPC_IOD_COMB_RANGE | LPC_IOD_COMA_RANGE);
+	uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMB_EN | LPC_IOE_COMA_EN);
+
+	/* Open IO windows: 0x3f8 for com1 and 02e8 for com2 */
+	pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod);
+	/* LPC I/O enable: com1 and com2 */
+	pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe);
+
+	/* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */
+	pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod);
+	pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe);
+}
+
+static uint8_t com_to_ast_sio(uint8_t com)
+{
+	switch (com) {
+	case 0:
+		return AST2400_SUART1;
+	case 1:
+		return AST2400_SUART2;
+	case 2:
+		return AST2400_SUART3;
+	case 4:
+		return AST2400_SUART4;
+	default:
+		return AST2400_SUART1;
+	}
+}
+
+void bootblock_mainboard_early_init(void)
+{
+	/* Open IO windows */
+	enable_espi_lpc_io_windows();
+
+	/* Configure appropriate physical port of SuperIO chip off BMC */
+	const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT,
+		com_to_ast_sio(CONFIG_UART_FOR_CONSOLE));
+	aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
+}