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author | Matt DeVillier <matt.devillier@gmail.com> | 2018-03-02 14:22:14 -0500 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-26 10:21:07 +0000 |
commit | 6dd4f76c77af8b12a7dc5d617b9c72f63ea1352f (patch) | |
tree | c59721c42df1e2cc98c367cccfb765194752a5bf /src/mainboard/nvidia | |
parent | ea5c0a15abcc7fda2f95b83a40ab3bd879ae2f0b (diff) |
soc/skylake/cpu: Fix Intel SpeedStep enable/disable
In an attempt at consolidation, commit 0a203d1 [1] introduced
an additional read/write of the MISC_ENABLE msr, as well a bug
which nullified the setting of Intel SpeedStep by inserting said
read/write calls in between another set of read/write calls to the
same msr. Fix by reverting to previous (simpler) implementation.
[1] soc/intel/skylake: Use CPU common library code
https://review.coreboot.org/19566
Test: boot Linux on Librem13v2, read MISC_ENABLE msr and verify
SpeedStep bit correctly set based on devicetree setting.
Change-Id: Id2ac660bf8ea56d45e8c3f631a586b74106a6cc9
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/nvidia')
0 files changed, 0 insertions, 0 deletions