diff options
| author | Keith Hui <buurin@gmail.com> | 2017-08-13 16:31:18 -0400 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-08-21 17:02:45 +0000 |
| commit | bb73c98d24f10941b060df983b0c8b7169f6a25e (patch) | |
| tree | 2b966409a4119e57ec24f3a1a971dbeb24988d4a /src/mainboard/nvidia/l1_2pvv | |
| parent | 928c6c6336f2f04a7bd2d489ac9901aa0d7dfa2a (diff) | |
Boards w/ Winbond superios: Use common config entry code
Six mainboards with Winbond superios directly configure
them in romstage.c. All use the common Winbond romstage
code. Change them to use the common config entry code to
allow for code refactoring such as [1]. Build tested.
[1] https://review.coreboot.org/20988
Change-Id: Icecd52ec622b9da86edb07c52893f4db001e5562
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/nvidia/l1_2pvv')
| -rw-r--r-- | src/mainboard/nvidia/l1_2pvv/romstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index d8076f0b79..c2fd79858c 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -124,9 +124,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - pnp_enter_ext_func_mode(SERIAL_DEV); + pnp_enter_conf_state(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x24, 0); - pnp_exit_ext_func_mode(SERIAL_DEV); + pnp_exit_conf_state(SERIAL_DEV); setup_mb_resource_map(); |