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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-01-17 15:27:18 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2018-01-18 20:46:48 +0000
commit8f274e147a24f0b877420dc045625e47705b4ed9 (patch)
tree6881b0c20bbf93769d749a8dbe5dc4d8513ef75e /src/mainboard/nokia/ip530
parent4c65398c10fa4583ad6b83ddc7f7873625a6ddbf (diff)
Intel i440bx boards: Remove - using LATE_CBMEM_INIT
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. Mainboards: src/mainboard/a-trend/atc-6220 src/mainboard/a-trend/atc-6240 src/mainboard/abit/be6-ii_v2_0 src/mainboard/azza/pt-6ibd src/mainboard/biostar/m6tba src/mainboard/compaq/deskpro_en_sff_p600 src/mainboard/gigabyte/ga-6bxc src/mainboard/gigabyte/ga-6bxe src/mainboard/msi/ms6119 src/mainboard/msi/ms6147 src/mainboard/msi/ms6156 src/mainboard/nokia/ip530 src/mainboard/soyo/sy-6ba-plus-iii src/mainboard/tyan/s1846 Change-Id: Id895963f9641bcaaa65e8a8cb21213a758a9ad80 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23301 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/nokia/ip530')
-rw-r--r--src/mainboard/nokia/ip530/Kconfig43
-rw-r--r--src/mainboard/nokia/ip530/Kconfig.name2
-rw-r--r--src/mainboard/nokia/ip530/board_info.txt5
-rw-r--r--src/mainboard/nokia/ip530/devicetree.cb112
-rw-r--r--src/mainboard/nokia/ip530/irq_tables.c92
-rw-r--r--src/mainboard/nokia/ip530/romstage.c42
6 files changed, 0 insertions, 296 deletions
diff --git a/src/mainboard/nokia/ip530/Kconfig b/src/mainboard/nokia/ip530/Kconfig
deleted file mode 100644
index 5584988580..0000000000
--- a/src/mainboard/nokia/ip530/Kconfig
+++ /dev/null
@@ -1,43 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-if BOARD_NOKIA_IP530
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_INTEL_SOCKET_PGA370
- select NORTHBRIDGE_INTEL_I440BX
- select LATE_CBMEM_INIT
- select SOUTHBRIDGE_INTEL_I82371EB
- select SUPERIO_SMSC_SMSCSUPERIO
- select SOUTHBRIDGE_TI_PCI1X2X
- select DRIVERS_DEC_21143
- select BOARD_ROMSIZE_KB_512
- select PIRQ_ROUTE
- select HAVE_PIRQ_TABLE
- select SDRAMPWR_4DIMM
-
-config MAINBOARD_DIR
- string
- default nokia/ip530
-
-config MAINBOARD_PART_NUMBER
- string
- default "IP530"
-
-config IRQ_SLOT_COUNT
- int
- default 22
-
-endif # BOARD_NOKIA_IP530
diff --git a/src/mainboard/nokia/ip530/Kconfig.name b/src/mainboard/nokia/ip530/Kconfig.name
deleted file mode 100644
index 22367d35ad..0000000000
--- a/src/mainboard/nokia/ip530/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_NOKIA_IP530
- bool "IP530"
diff --git a/src/mainboard/nokia/ip530/board_info.txt b/src/mainboard/nokia/ip530/board_info.txt
deleted file mode 100644
index f9285bf9df..0000000000
--- a/src/mainboard/nokia/ip530/board_info.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-Category: server
-ROM package: TSOP48
-ROM protocol: Parallel
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/nokia/ip530/devicetree.cb b/src/mainboard/nokia/ip530/devicetree.cb
deleted file mode 100644
index 8de81bbcf5..0000000000
--- a/src/mainboard/nokia/ip530/devicetree.cb
+++ /dev/null
@@ -1,112 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-chip northbridge/intel/i440bx # Northbridge
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/intel/socket_PGA370 # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
- device domain 0 on # PCI domain
- device pci 0.0 on end # Host bridge
- device pci 1.0 on end # PCI/AGP bridge
- chip southbridge/intel/i82371eb # Southbridge
- device pci f.0 on
- chip southbridge/ti/pci1x2x
- device pci 00.0 on
- subsystemid 0x13b8 0x0000
- end
- register "scr" = "0x08449060"
- register "mrr" = "0x00007522"
- end
- end
- device pci 7.0 on # ISA bridge
- chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37B787)
- device pnp 3f0.0 off end # Floppy (No connector)
- device pnp 3f0.3 off end # Parallel port (No connector)
- device pnp 3f0.4 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 3f0.5 on # COM2 / IR
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 3f0.6 on # RTC
- irq 0x63 = 0x72
- end
- device pnp 3f0.7 off # PS/2 keyboard / mouse (No connector)
- end
- device pnp 3f0.8 on # AUX I/O
- irq 0x24 = 0x84 # OSC
-
- irq 0xB2 = 0x0C # Soft power status 1
- irq 0xB3 = 0x05 # Soft power status 2
- irq 0xC0 = 0x03 # IRQ MUX control
-
- irq 0xC8 = 0x10 # GP50 = (I/O) output = Flashrom enable
- irq 0xCA = 0x09 # GP52 = IRQ8 (output)
- irq 0xCB = 0x01 # GP53 = nROMCS (output)
- irq 0xCC = 0x11 # GP54 = (I/O) input
- irq 0xF9 = 0x00 # read/write GP5x lines (0x1C)
-
- irq 0xD0 = 0x08 # GP60 = IRQ1
- irq 0xD1 = 0x08 # GP61 = IRQ3
- irq 0xD2 = 0x08 # GP62 = IRQ4
- irq 0xD3 = 0x11 # GP63 = (I/O) input = JP901 on board
- irq 0xD4 = 0x11 # GP64 = (I/O) input
- irq 0xD5 = 0x11 # GP65 = (I/O) input
- irq 0xD6 = 0x08 # GP66 = IRQ8
- irq 0xD7 = 0x11 # GP67 = (I/O) input
- irq 0xFA = 0x00 # read/write GP6x lines (0x88)
-
- irq 0xE0 = 0x00 # GP10 (I/O) = output
- irq 0xE1 = 0x01 # GP11 (I/O) = input
- irq 0xE2 = 0x08 # GP12 = P17
- irq 0xE3 = 0x00 # GP13 (I/O) = output = LED fault on front, active low
- irq 0xE4 = 0x00 # GP14 (I/O) = output
- irq 0xE5 = 0x00 # GP15 (I/O) = output
- irq 0xE6 = 0x01 # GP16 (I/O) = input = JP900 on board, low on short, high on open
- irq 0xE7 = 0x00 # GP17 (I/O) = output = LED alert on front, active low
- irq 0xF6 = 0xFF # read/write GP1x lines (0xCA)
-
- irq 0xEF = 0x00 # GP_INT2 disable
- irq 0xF0 = 0x00 # GP_INT1 disable
- irq 0xF1 = 0x00 # WDT_UNITS
- irq 0xF2 = 0x00 # WDT_VAL
- irq 0xF3 = 0x00 # WDT_CFG
- irq 0xF4 = 0x20 # WDT_CTRL (stop-cnt)
- end
- device pnp 3f0.a off # ACPI (No support yet)
- # irq 0x60 = 0x0C
- # irq 0x61 = 0x80
- end
- end
- end
- device pci 7.1 on end # IDE
- device pci 7.2 off end # USB (No connector)
- device pci 7.3 off end # ACPI (No support yet)
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- register "ide_legacy_enable" = "1"
- # Disable UDMA/33 for lower speed if your IDE device(s) don't support it.
- register "ide0_drive0_udma33_enable" = "1"
- register "ide0_drive1_udma33_enable" = "1"
- register "ide1_drive0_udma33_enable" = "1"
- register "ide1_drive1_udma33_enable" = "1"
- end
- end
-end
diff --git a/src/mainboard/nokia/ip530/irq_tables.c b/src/mainboard/nokia/ip530/irq_tables.c
deleted file mode 100644
index f14fac2776..0000000000
--- a/src/mainboard/nokia/ip530/irq_tables.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-
-#define PIRQ_IRQ_MASK 0x0c60
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
- 0x00, /* Interrupt router bus */
- (0x07 << 3) | 0x0, /* Interrupt router dev */
- 0, /* IRQs devoted exclusively to PCI usage */
- 0x8086, /* Vendor */
- 0x122e, /* Device */
- 0, /* Miniport */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0xD7, /* Checksum */
- {
- /**
- * Rebuild of the PIRQ table, to fix the non-working on-board NIC and PCMCIA controller.
- * FEDCBA9876543210
- * 0x1E20 = 0001111000100000
- * 0x0C60 = 0000110001100000
- */
- // Southbridge 82371EB, INTD = 0x63
- { 0x00, (0x07 << 3) | 0x0, {{0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
- // On-board PCI-to-PCI bridge
- { 0x01, (0x00 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
- // ETH1 on front panel, INTA = 0x62 = ok
- { 0x00, (0x0d << 3) | 0x0, {{0x62, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
-
- // ETH2 on front panel, 0x63
- { 0x00, (0x0e << 3) | 0x0, {{0x63, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
- // ETH3 on front panel = 0x60
- { 0x02, (0x04 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
-
- // ETH4 on front panel, INTA = 0x61 = ok
- { 0x02, (0x05 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
- // PCMCIA/Cardbus controller, INTA = 0x60 = ok, INTB = 0x61 = ok
- { 0x00, (0x0f << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
- // Bridge for slot 1 (top)
- { 0x02, (0x07 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x64, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
- // PCI compact slots 1 (top)
- { 0x03, (0x04 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x1, 0x0 },
- { 0x03, (0x05 << 3) | 0x0, {{0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}}, 0x2, 0x0 },
- { 0x03, (0x06 << 3) | 0x0, {{0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}}, 0x3, 0x0 },
- { 0x03, (0x07 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}}, 0x4, 0x0 },
- // Bridge for slot 2 (middle)
- { 0x02, (0x06 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
- // PCI compact slots 2 (middle)
- { 0x04, (0x04 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x5, 0x0 },
- { 0x04, (0x05 << 3) | 0x0, {{0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}}, 0x6, 0x0 },
- { 0x04, (0x06 << 3) | 0x0, {{0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}}, 0x7, 0x0 },
- { 0x04, (0x07 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}}, 0x8, 0x0 },
- // Bridge for slot 3 (bottom)
- { 0x00, (0x10 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
- // PCI compact slots 3 (bottom)
- { 0x05, (0x04 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x9, 0x0 },
- { 0x05, (0x05 << 3) | 0x0, {{0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}}, 0xA, 0x0 },
- { 0x05, (0x06 << 3) | 0x0, {{0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}}, 0xB, 0x0 },
- { 0x05, (0x07 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}}, 0xC, 0x0 },
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
-
-/**
- * TODO: This stub function is here until the point is solved in the
- * main code of coreboot. See also arch/x86/boot/pirq_tables.c.
- */
-void pirq_assign_irqs(const unsigned char pIntAtoD[4])
-{
- return;
-}
diff --git a/src/mainboard/nokia/ip530/romstage.c b/src/mainboard/nokia/ip530/romstage.c
deleted file mode 100644
index fa0585dbfe..0000000000
--- a/src/mainboard/nokia/ip530/romstage.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/pci_def.h>
-#include <device/pnp_def.h>
-#include <console/console.h>
-#include <southbridge/intel/i82371eb/i82371eb.h>
-#include <northbridge/intel/i440bx/raminit.h>
-#include <cpu/x86/bist.h>
-#include <cpu/intel/romstage.h>
-#include <superio/smsc/smscsuperio/smscsuperio.h>
-#include <lib.h>
-
-#define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1)
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
- return smbus_read_byte(device, address);
-}
-
-void mainboard_romstage_entry(unsigned long bist)
-{
- smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
- report_bist_failure(bist);
-
- enable_smbus();
- sdram_initialize();
-}