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authorArthur Heymans <arthur@aheymans.xyz>2019-11-19 15:55:05 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-20 18:58:43 +0000
commitf2e42c4a8ec75c162251c72df8ac3da12e8a3eb9 (patch)
treefd5851ba2be3965df592355d02bce01f7dab0215 /src/mainboard/msi
parentad983eeec76ecdb2aff4fb47baeee95ade012225 (diff)
mb/*/*: Drop AMDFAM10 mainboards
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Ic00ca18de3d73a17041a3a2839307149ad7902b2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36961 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/msi')
-rw-r--r--src/mainboard/msi/ms9652_fam10/Kconfig83
-rw-r--r--src/mainboard/msi/ms9652_fam10/Kconfig.name2
-rw-r--r--src/mainboard/msi/ms9652_fam10/Makefile.inc16
-rw-r--r--src/mainboard/msi/ms9652_fam10/acpi/util.asl329
-rw-r--r--src/mainboard/msi/ms9652_fam10/acpi_tables.c80
-rw-r--r--src/mainboard/msi/ms9652_fam10/board_info.txt2
-rw-r--r--src/mainboard/msi/ms9652_fam10/cmos.layout102
-rw-r--r--src/mainboard/msi/ms9652_fam10/devicetree.cb165
-rw-r--r--src/mainboard/msi/ms9652_fam10/dsdt.asl298
-rw-r--r--src/mainboard/msi/ms9652_fam10/get_bus_conf.c80
-rw-r--r--src/mainboard/msi/ms9652_fam10/hda_verb.c20
-rw-r--r--src/mainboard/msi/ms9652_fam10/irq_tables.c137
-rw-r--r--src/mainboard/msi/ms9652_fam10/mb_sysconf.h26
-rw-r--r--src/mainboard/msi/ms9652_fam10/mptable.c113
-rw-r--r--src/mainboard/msi/ms9652_fam10/resourcemap.c285
-rw-r--r--src/mainboard/msi/ms9652_fam10/romstage.c271
16 files changed, 0 insertions, 2009 deletions
diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig
deleted file mode 100644
index 22f655a116..0000000000
--- a/src/mainboard/msi/ms9652_fam10/Kconfig
+++ /dev/null
@@ -1,83 +0,0 @@
-if BOARD_MSI_MS9652_FAM10
-
-config BOARD_SPECIFIC_OPTIONS
- def_bool y
- select CPU_AMD_SOCKET_F_1207
- select DIMM_DDR2
- select DIMM_REGISTERED
- select NORTHBRIDGE_AMD_AMDFAM10
- select SOUTHBRIDGE_NVIDIA_MCP55
- select MCP55_USE_NIC
- select MCP55_USE_AZA
- select SUPERIO_WINBOND_W83627EHG
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select HAVE_ACPI_TABLES
- select HAVE_OPTION_TABLE
- select BOARD_ROMSIZE_KB_512
- select ENABLE_APIC_EXT_ID
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select LIFT_BSP_APIC_ID
- select IOAPIC
- select SMP
- select POWER_STATE_DEFAULT_ON_AFTER_FAILURE
-
-config MAINBOARD_DIR
- string
- default msi/ms9652_fam10
-
-config DCACHE_RAM_BASE
- hex
- default 0xc4000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x0c000
-
-# Define to 0 because the IRQ slot count is
-# determined dynamically for this board.
-config IRQ_SLOT_COUNT
- int
- default 0
-
-config MAX_CPUS
- int
- default 8
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config USE_OPTION_TABLE
- bool
- default n
-
-config MAINBOARD_PART_NUMBER
- string
- default "MS-9652"
-
-config DEFAULT_CONSOLE_LOGLEVEL
- int
- default 9
-
-config USBDEBUG
- bool
- default n
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x20
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x00
-
-config APIC_ID_OFFSET
- hex
- default 0x00
-
-config MCP55_PCI_E_X_0
- int
- default 1
-
-endif # BOARD_MSI_MS9652_FAM10
diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig.name b/src/mainboard/msi/ms9652_fam10/Kconfig.name
deleted file mode 100644
index 3c6659c857..0000000000
--- a/src/mainboard/msi/ms9652_fam10/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_MSI_MS9652_FAM10
- bool "MS-9652 Fam10 (Speedster K9ND)"
diff --git a/src/mainboard/msi/ms9652_fam10/Makefile.inc b/src/mainboard/msi/ms9652_fam10/Makefile.inc
deleted file mode 100644
index 91d4b39c32..0000000000
--- a/src/mainboard/msi/ms9652_fam10/Makefile.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-romstage-y += resourcemap.c
-
-ramstage-y += get_bus_conf.c
diff --git a/src/mainboard/msi/ms9652_fam10/acpi/util.asl b/src/mainboard/msi/ms9652_fam10/acpi/util.asl
deleted file mode 100644
index d272233d2d..0000000000
--- a/src/mainboard/msi/ms9652_fam10/acpi/util.asl
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2005 AMD
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-//AMD k8 util for BUSB and res range
-
-Scope (\_SB)
-{
-
- Name (OSTB, Ones)
- Method (OSVR, 0, NotSerialized)
- {
- If (LEqual (^OSTB, Ones))
- {
- Store (0x00, ^OSTB)
- }
-
- Return (^OSTB)
- }
-
- Method (SEQL, 2, Serialized)
- {
- Store (SizeOf (Arg0), Local0)
- Store (SizeOf (Arg1), Local1)
- If (LNot (LEqual (Local0, Local1))) { Return (Zero) }
-
- Name (BUF0, Buffer (Local0) {})
- Store (Arg0, BUF0)
- Name (BUF1, Buffer (Local0) {})
- Store (Arg1, BUF1)
- Store (Zero, Local2)
- While (LLess (Local2, Local0))
- {
- Store (DerefOf (Index (BUF0, Local2)), Local3)
- Store (DerefOf (Index (BUF1, Local2)), Local4)
- If (LNot (LEqual (Local3, Local4))) { Return (Zero) }
-
- Increment (Local2)
- }
-
- Return (One)
- }
-
-
- Method (DADD, 2, NotSerialized)
- {
- Store(Arg1, Local0)
- Store(Arg0, Local1)
- Add(ShiftLeft(Local1,16), Local0, Local0)
- Return (Local0)
- }
-
-
- Method (GHCE, 1, NotSerialized) // check if the HC enabled
- {
- Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
- if (LEqual (And(Local1, 0x01), 0x01)) { Return (0x0F) }
- Else { Return (0x00) }
- }
-
- Method (GHCN, 1, NotSerialized) // get the node num for the HC
- {
- Store (0x00, Local0)
- Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
- Store (ShiftRight(And (Local1, 0xf0), 0x04), Local0)
- Return (Local0)
- }
-
- Method (GHCL, 1, NotSerialized) // get the link num on node for the HC
- {
- Store (0x00, Local0)
- Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
- Store (ShiftRight(And (Local1, 0xf00), 0x08), Local0)
- Return (Local0)
- }
-
- Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC
- {
- Store (0x00, Local0)
- Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1)
- Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0
- Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0
- Store (And (ShiftRight(Local1, Local2), 0xff), Local0)
- Return (Local0)
- }
-
- /* GetBus(Node, Link) */
- Method (GBUS, 2, NotSerialized)
- {
- Store (0x00, Local0)
- While (LLess (Local0, 0x04))
- {
- Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
- If (LEqual (And (Local1, 0x03), 0x03))
- {
- If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
- {
- If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
- {
- Return (ShiftRight (And (Local1, 0x00FF0000), 0x10))
- }
- }
- }
-
- Increment (Local0)
- }
-
- Return (0x00)
- }
-
- /* GetBusResources(Node, Link) */
- Method (GWBN, 2, Serialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0000, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0001,,,)
- })
- CreateWordField (BUF0, 0x08, BMIN)
- CreateWordField (BUF0, 0x0A, BMAX)
- CreateWordField (BUF0, 0x0E, BLEN)
- Store (0x00, Local0)
- While (LLess (Local0, 0x04))
- {
- Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
- If (LEqual (And (Local1, 0x03), 0x03))
- {
- If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
- {
- If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
- {
- Store (ShiftRight (And (Local1, 0x00FF0000), 0x10), BMIN)
- Store (ShiftRight (Local1, 0x18), BMAX)
- Subtract (BMAX, BMIN, BLEN)
- Increment (BLEN)
- Return (RTAG (BUF0))
- }
- }
- }
-
- Increment (Local0)
- }
-
- Return (RTAG (BUF0))
- }
-
- /* GetMemoryResources(Node, Link) */
- Method (GMEM, 2, Serialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
- 0x00000000, // Address Space Granularity
- 0x00000000, // Address Range Minimum
- 0x00000000, // Address Range Maximum
- 0x00000000, // Address Translation Offset
- 0x00000001,,,
- , AddressRangeMemory, TypeStatic)
- })
- CreateDWordField (BUF0, 0x0A, MMIN)
- CreateDWordField (BUF0, 0x0E, MMAX)
- CreateDWordField (BUF0, 0x16, MLEN)
- Store (0x00, Local0)
- Store (0x00, Local4)
- Store (0x00, Local3)
- While (LLess (Local0, 0x10))
- {
- /* Get value of the first register */
- Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1)
- Increment (Local0)
- Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2)
- If (LEqual (And (Local1, 0x03), 0x03)) /* Pair enabled? */
- {
- If (LEqual (Arg0, And (Local2, 0x07))) /* Node matches? */
- {
- /* If Link Matches (or we got passed 0xFF) */
- If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
- {
- /* Extract the Base and Limit values */
- Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN)
- Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX)
- Or (MMAX, 0xFFFF, MMAX)
- Subtract (MMAX, MMIN, MLEN)
- Increment (MLEN)
-
- If (Local4) /* I've already done this once */
- {
- Concatenate (RTAG (BUF0), Local3, Local5)
- Store (Local5, Local3)
- }
- Else
- {
- Store (RTAG (BUF0), Local3)
- }
-
- Increment (Local4)
- }
- }
- }
-
- Increment (Local0)
- }
-
- If (LNot (Local4)) /* No resources for this node and link. */
- {
- Store (RTAG (BUF0), Local3)
- }
-
- Return (Local3)
- }
-
- /* GetIOResources(Node, Link) */
- Method (GIOR, 2, Serialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x00000000, // Address Space Granularity
- 0x00000000, // Address Range Minimum
- 0x00000000, // Address Range Maximum
- 0x00000000, // Address Translation Offset
- 0x00000001,,,
- , TypeStatic)
- })
- CreateDWordField (BUF0, 0x0A, PMIN)
- CreateDWordField (BUF0, 0x0E, PMAX)
- CreateDWordField (BUF0, 0x16, PLEN)
- Store (0x00, Local0)
- Store (0x00, Local4)
- Store (0x00, Local3)
- While (LLess (Local0, 0x08))
- {
- Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1)
- Increment (Local0)
- Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2)
- If (LEqual (And (Local1, 0x03), 0x03)) /* Pair enabled? */
- {
- If (LEqual (Arg0, And (Local2, 0x07))) /* Node matches? */
- {
- /* If Link Matches (or we got passed 0xFF) */
- If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
- {
- /* Extract the Base and Limit values */
- Store (And (Local1, 0x01FFF000), PMIN)
- Store (And (Local2, 0x01FFF000), PMAX)
- Or (PMAX, 0x0FFF, PMAX)
- Subtract (PMAX, PMIN, PLEN)
- Increment (PLEN)
-
- If (Local4) /* I've already done this once */
- {
- Concatenate (RTAG (BUF0), Local3, Local5)
- Store (Local5, Local3)
- }
- Else
- {
- If (LGreater (PMAX, PMIN))
- {
- If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK)))
- {
- Store (0x0D00, PMIN)
- Subtract (PMAX, PMIN, PLEN)
- Increment (PLEN)
- }
-
- Store (RTAG (BUF0), Local3)
- Increment (Local4)
- }
-
- If (And (Local1, 0x10))
- {
- Store (0x03B0, PMIN)
- Store (0x03DF, PMAX)
- Store (0x30, PLEN)
-
- If (Local4)
- {
- Concatenate (RTAG (BUF0), Local3, Local5)
- Store (Local5, Local3)
- }
- Else
- {
- Store (RTAG (BUF0), Local3)
- }
- }
- }
-
- Increment (Local4)
- }
- }
- }
-
- Increment (Local0)
- }
-
- If (LNot (Local4)) /* No resources for this node and link. */
- {
- Store (RTAG (BUF0), Local3)
- }
-
- Return (Local3)
- }
-
- Method (RTAG, 1, NotSerialized)
- {
- Store (Arg0, Local0)
- Store (SizeOf (Local0), Local1)
- Subtract (Local1, 0x02, Local1)
- Multiply (Local1, 0x08, Local1)
- CreateField (Local0, 0x00, Local1, RETB)
- Store (RETB, Local2)
- Return (Local2)
- }
-}
diff --git a/src/mainboard/msi/ms9652_fam10/acpi_tables.c b/src/mainboard/msi/ms9652_fam10/acpi_tables.c
deleted file mode 100644
index 9f230df518..0000000000
--- a/src/mainboard/msi/ms9652_fam10/acpi_tables.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Written by Stefan Reinauer <stepan@openbios.org>.
- * ACPI FADT, FACS, and DSDT table support added by
- *
- * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
- * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2009 Harald Gutmann <harald.gutmann@gmx.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <cpu/amd/powernow.h>
-#include <device/pci.h>
-#include <cpu/amd/amdfam10_sysconf.h>
-#include "mb_sysconf.h"
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- unsigned int gsi_base = 0x18;
- struct mb_sysconf_t *m;
- //extern unsigned char bus_mcp55[8];
- //extern unsigned apicid_mcp55;
-
- unsigned int sbdn;
- struct resource *res;
- struct device *dev;
-
- sbdn = sysconf.sbdn;
- m = sysconf.mb;
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB IOAPIC. */
- dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- m->apicid_mcp55, res->base, 0);
- }
- }
-
- /* Write NB IOAPIC. */
- dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x12,1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- m->apicid_mcp55++, res->base, gsi_base);
- }
- }
-
- /* IRQ9 ACPI active low. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-
- /* IRQ0 -> APIC IRQ2. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0x0);
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapic_nmis(current,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
- return current;
-}
diff --git a/src/mainboard/msi/ms9652_fam10/board_info.txt b/src/mainboard/msi/ms9652_fam10/board_info.txt
deleted file mode 100644
index eb2dda33a8..0000000000
--- a/src/mainboard/msi/ms9652_fam10/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Category: desktop
-Release year: 2007
diff --git a/src/mainboard/msi/ms9652_fam10/cmos.layout b/src/mainboard/msi/ms9652_fam10/cmos.layout
deleted file mode 100644
index 331e0162bb..0000000000
--- a/src/mainboard/msi/ms9652_fam10/cmos.layout
+++ /dev/null
@@ -1,102 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-393 3 r 0 unused
-#394 7 unused
-401 1 e 1 interleave_chip_selects
-402 1 e 1 interleave_nodes
-403 1 e 1 interleave_memory_channels
-404 2 e 8 max_mem_clock
-406 1 e 2 multi_core
-412 4 e 6 debug_level
-416 5 e 10 ecc_scrub_rate
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 gart
-446 1 e 1 power_on_after_fail
-456 1 e 1 ECC_memory
-457 1 e 1 ECC_redirection
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 0 Emergency
-6 1 Alert
-6 2 Critical
-6 3 Error
-6 4 Warning
-6 5 Notice
-6 6 Information
-6 7 Debug
-6 8 Spew
-8 0 DDR2-800
-8 1 DDR2-667
-8 2 DDR2-533
-8 3 DDR2-400
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-10 0 Disabled
-10 1 40ns
-10 2 80ns
-10 3 160ns
-10 4 320ns
-10 5 640ns
-10 6 1.28us
-10 7 2.56us
-10 8 5.12us
-10 9 10.2us
-10 10 20.5us
-10 11 41us
-10 12 81.9us
-10 13 163.8us
-10 14 327.7us
-10 15 655.4us
-10 16 1.31ms
-10 17 2.62ms
-10 18 5.24ms
-10 19 10.49ms
-10 20 20.97sms
-10 21 42ms
-10 22 84ms
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/msi/ms9652_fam10/devicetree.cb b/src/mainboard/msi/ms9652_fam10/devicetree.cb
deleted file mode 100644
index c6dae6d451..0000000000
--- a/src/mainboard/msi/ms9652_fam10/devicetree.cb
+++ /dev/null
@@ -1,165 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-## Copyright (C) 2010 Raptor Engineering
-## Written by Timothy Pearson <tpearson@raptorengineeringinc.com> for Raptor Engineering.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-chip northbridge/amd/amdfam10/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_F_1207 # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x1462 0x9652 inherit
- chip northbridge/amd/amdfam10 # Northbridge / RAM controller
- device pci 18.0 on # Link 0
- chip southbridge/nvidia/mcp55 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/winbond/w83627ehg # Super I/O
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # PS/2 keyboard & mouse
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.106 off # Serial flash interface (SFI)
- io 0x60 = 0x100
- end
- device pnp 2e.007 off # GPIO 1
- end
- device pnp 2e.107 on # Game port
- io 0x60 = 0x220
- end
- device pnp 2e.207 on # MIDI
- io 0x62 = 0x330
- irq 0x70 = 0xa
- end
- device pnp 2e.307 off # GPIO 6
- end
- device pnp 2e.8 off # WDTO#, PLED
- end
- device pnp 2e.009 off # GPIO 2
- end
- device pnp 2e.109 off # GPIO 3
- end
- device pnp 2e.209 off # GPIO 4
- end
- device pnp 2e.309 off # GPIO 5
- end
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # Hardware monitor
- io 0x60 = 0x290
- irq 0x70 = 5
- end
- end
- end
- device pci 1.1 on # SM 0
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- chip drivers/generic/generic # DIMM 1-0-0
- device i2c 54 on end
- end
- chip drivers/generic/generic # DIMM 1-0-1
- device i2c 55 on end
- end
- chip drivers/generic/generic # DIMM 1-1-0
- device i2c 56 on end
- end
- chip drivers/generic/generic # DIMM 1-1-1
- device i2c 57 on end
- end
- end
- device pci 1.1 on # SM 1
- # PCI device SMBus address will
- # depend on addon PCI device, do
- # we need to scan_smbus_bus?
- # chip drivers/generic/generic # PCIXA slot 1
- # device i2c 50 on end
- # end
- # chip drivers/generic/generic # PCIXB slot 1
- # device i2c 51 on end
- # end
- # chip drivers/generic/generic # PCIXB slot 2
- # device i2c 52 on end
- # end
- # chip drivers/generic/generic # PCI slot 1
- # device i2c 53 on end
- # end
- # chip drivers/generic/generic # Master MCP55 PCI-E
- # device i2c 54 on end
- # end
- # chip drivers/generic/generic # Slave MCP55 PCI-E
- # device i2c 55 on end
- # end
- # chip drivers/generic/generic # MAC EEPROM
- # device i2c 51 on end
- # end
- end
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # IDE
- device pci 5.0 on end # SATA 0
- device pci 5.1 on end # SATA 1
- device pci 5.2 on end # SATA 2
- device pci 6.1 on end # AZA
- device pci 8.0 on end # NIC
- device pci 9.0 on end # NIC
- register "ide0_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- # 1: SMBus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
- end
- end
- device pci 18.0 on end # HT 1.0
- device pci 18.0 on end # HT 2.0
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- device pci 18.4 on end
- end
- end
-end
diff --git a/src/mainboard/msi/ms9652_fam10/dsdt.asl b/src/mainboard/msi/ms9652_fam10/dsdt.asl
deleted file mode 100644
index 2115f4cc44..0000000000
--- a/src/mainboard/msi/ms9652_fam10/dsdt.asl
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2009 Harald Gutmann <harald.gutmann@gmx.net>
- *
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-DefinitionBlock ("DSDT.aml", "DSDT", 1, OEM_ID, ACPI_TABLE_CREATOR, 1)
-{
- #include "acpi/util.asl"
-
- /* For now only define 2 power states:
- * - S0 which is fully on
- * - S5 which is soft off
- */
- Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
- Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 })
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- */
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- /* PCI Routing Table */
- Name (_PRT, Package () {
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0A }, /* 0x1 - 00:01.1 - IRQ 10 - SMBus */
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x16 }, /* 0x2 - 00:02.0 - IRQ 22 - USB */
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x17 }, /* 0x2 - 00:01.1 - IRQ 23 - USB */
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x15 }, /* 0x4 - 00:04.0 - IRQ 21 - IDE */
- Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x14 }, /* 0x5 - 00:05.0 - IRQ 20 - SATA */
- Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x15 }, /* 0x5 - 00:05.1 - IRQ 21 - SATA */
- Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 }, /* 0x5 - 00:05.2 - IRQ 22 - SATA */
- Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x17 }, /* 0x6 - 00:06.1 - IRQ 23 - HD Audio */
- Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 }, /* 0x8 - 00:08.0 - IRQ 20 - GBit Ethernet */
- })
-
- Device (PEBF) /* PCI-E Bridge F */
- {
- Name (_ADR, 0x000F0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x07)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
- })
- }
-
- Device (PEBE) /* PCI-E Bridge E */
- {
- Name (_ADR, 0x000E0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x06)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
- })
- }
-
- Device (PEBD) /* PCI-E Bridge D */
- {
- Name (_ADR, 0x000D0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x05)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x13 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x12 },
- })
- }
-
- Device (PEBC) /* PCI-E Bridge C */
- {
- Name (_ADR, 0x000C0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x04)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
- })
- }
-
- Device (PEBB) /* PCI-E Bridge B */
- {
- Name (_ADR, 0x000B0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x03)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
- })
- }
-
- Device (PEBA) /* PCI-E Bridge A */
- {
- Name (_ADR, 0x000A0000)
- Name (_UID, 0x00)
- Name (_BBN, 0x02)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
- })
- }
-
- Device (PCID) /* PCI Device */
- {
- Name (_ADR, 0x00060000)
- Name (_UID, 0x00)
- Name (_BBN, 0x01)
- Name (_PRT, Package () {
- Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x12 },
- Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x11 },
- Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x13 }, /* PCI slot 1 */
- Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x10 },
- Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x11 },
- Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x12 },
- Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x10 }, /* PCI slot 2 */
- Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x13 },
- Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x11 },
- Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x10 },
- Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x12 }, /* FireWire */
- Package (0x04) { 0x000AFFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x000AFFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x000AFFFF, 0x03, 0x00, 0x11 },
- })
- }
- }
-
- Device (ISA) {
- Name (_ADR, 0x000010000)
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP0, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP0)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP1, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {12}
- })
- Return (TMP1)
- }
- }
-
- /* PS/2 floppy controller */
- Device (FDC0)
- {
- Name (_HID, EisaId ("PNP0700"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () {
- IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)
- IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01)
- IRQNoFlags () {6}
- DMA (Compatibility, NotBusMaster, Transfer8) {2}
- })
- Return (BUF0)
- }
- }
- /* Parallel Port */
- Device (LPT1)
- {
- Name (_HID, EisaId ("PNP0400"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF1, ResourceTemplate () {
- IO (Decode16, 0x0378, 0x0378, 0x01, 0x08)
- IRQNoFlags () {7}
- })
- Return (BUF1)
- }
- }
- /* Parallel Port ECP */
- Device (ECP1)
- {
- Name (_HID, EisaId ("PNP0401"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF1, ResourceTemplate () {
- IO (Decode16, 0x0378, 0x0378, 0x01, 0x04)
- IO (Decode16, 0x0778, 0x0778, 0x01, 0x04)
- IRQNoFlags() {7}
- DMA (Compatibility, NotBusMaster, Transfer8) {0,1,3}
- })
- Return (BUF1)
- }
- }
- }
- }
-}
diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
deleted file mode 100644
index d13a8130ed..0000000000
--- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdfam10_sysconf.h>
-
-#include <stdlib.h>
-#include "mb_sysconf.h"
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-struct mb_sysconf_t mb_sysconf;
-
-void get_bus_conf(void)
-{
- unsigned int apicid_base;
- struct mb_sysconf_t *m;
-
- struct device *dev;
- int i;
-
-
- sysconf.mb = &mb_sysconf;
-
- m = sysconf.mb;
- memset(m, 0, sizeof(struct mb_sysconf_t));
-
- get_default_pci1234(32);
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
- m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff;
-
- /* MCP55 */
- dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
- if (dev) {
- m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
- }
-
- for (i = 2; i < 8; i++) {
- dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));
- if (dev) {
- m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);
- }
- }
-
-/*I/O APICs: APIC ID Version State Address*/
- if (CONFIG(LOGICAL_CPUS)) {
- apicid_base = get_apicid_base(1);
- printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 1: apicid_base: %08x\n", apicid_base);
- } else {
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 0: apicid_base: %08x\n", apicid_base);
- }
- m->apicid_mcp55 = apicid_base+0;
-}
diff --git a/src/mainboard/msi/ms9652_fam10/hda_verb.c b/src/mainboard/msi/ms9652_fam10/hda_verb.c
deleted file mode 100644
index 5d088790a5..0000000000
--- a/src/mainboard/msi/ms9652_fam10/hda_verb.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[0] = {};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/msi/ms9652_fam10/irq_tables.c b/src/mainboard/msi/ms9652_fam10/irq_tables.c
deleted file mode 100644
index 69327dcafa..0000000000
--- a/src/mainboard/msi/ms9652_fam10/irq_tables.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdfam10_sysconf.h>
-#include "mb_sysconf.h"
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned int slot_num;
- uint8_t *v;
- struct mb_sysconf_t *m;
- unsigned int sbdn;
-
- uint8_t sum = 0;
- int i;
-
- sbdn = sysconf.sbdn;
- m = sysconf.mb;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = m->bus_mcp55[0];
- pirq->rtr_devfn = PCI_DEVFN(sbdn + 6, 0);
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x0370;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-//pci bridge
- write_pirq_info(pirq_info, m->bus_mcp55[0], PCI_DEVFN(sbdn + 6, 0), 0x1,
- 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
-
- for (i = 1; i < sysconf.hc_possible_num; i++) {
- if (!(sysconf.pci1234[i] & 0x1))
- continue;
- unsigned int busn = (sysconf.pci1234[i] >> 12) & 0xff;
- unsigned int devn = sysconf.hcdn[i] & 0xff;
-
- write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0xdef8,
- 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
- }
-
-#if CONFIG_CBB
- write_pirq_info(pirq_info, CONFIG_CBB, PCI_DEVFN(0, 0), 0x1, 0xdef8, 0x2,
- 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
- if (sysconf.nodes > 32) {
- write_pirq_info(pirq_info, CONFIG_CBB - 1, PCI_DEVFN(0, 0), 0x1,
- 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8,
- 0, 0);
- pirq_info++;
- slot_num++;
- }
-#endif
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/msi/ms9652_fam10/mb_sysconf.h b/src/mainboard/msi/ms9652_fam10/mb_sysconf.h
deleted file mode 100644
index 1a287c6a8a..0000000000
--- a/src/mainboard/msi/ms9652_fam10/mb_sysconf.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MB_SYSCONF_H
-#define MB_SYSCONF_H
-
-struct mb_sysconf_t {
- unsigned char bus_mcp55[8]; //1
- unsigned int apicid_mcp55;
-};
-
-#endif
diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c
deleted file mode 100644
index 6ae3de18f0..0000000000
--- a/src/mainboard/msi/ms9652_fam10/mptable.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <stdint.h>
-#include <cpu/amd/amdfam10_sysconf.h>
-#include "mb_sysconf.h"
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- struct mb_sysconf_t *m;
- unsigned int sbdn;
-
- int i, j, bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- sbdn = sysconf.sbdn;
- m = sysconf.mb;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs: APIC ID Version State Address*/
- {
- struct device *dev;
- struct resource *res;
- uint32_t dword;
-
- dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- smp_write_ioapic(mc, m->apicid_mcp55, 0x11,
- res2mmio(res, 0, 0));
- }
-
- dword = 0x43c6c643;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x81001a00;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0xd00012d2;
- pci_write_config32(dev, 0x84, dword);
-
- }
-
-
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
-
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 1, 1, m->apicid_mcp55, 0xa);
-
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 0, m->apicid_mcp55, 0x16); // 22)
-
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 1, m->apicid_mcp55, 0x17); // 23)
-
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 6, 1, m->apicid_mcp55, 0x17); // 23)
-
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 0, m->apicid_mcp55, 0x14); // 20)
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 1, m->apicid_mcp55, 0x17); // 23)
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 2, m->apicid_mcp55, 0x15); // 21)
-
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 8, 0, m->apicid_mcp55, 0x16); // 22)
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 9, 0, m->apicid_mcp55, 0x15); // 21)
-
- for (j = 7; j >= 2; j--) {
- if (!m->bus_mcp55[j])
- continue;
- for (i = 0; i < 4; i++)
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[j], 0x00, i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
- }
-
- for (j = 0; j < 1; j++)
- for (i = 0; i < 4; i++)
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[1], 0x04+j, i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/msi/ms9652_fam10/resourcemap.c b/src/mainboard/msi/ms9652_fam10/resourcemap.c
deleted file mode 100644
index 5d8aca7f8e..0000000000
--- a/src/mainboard/msi/ms9652_fam10/resourcemap.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <commonlib/helpers.h>
-#include <northbridge/amd/amdfam10/amdfam10.h>
-
-void setup_mb_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10
- ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
- ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
- ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
- ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
- ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
- ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
- ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
-
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10
- ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp address bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
- ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
- ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
- ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
- ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
- ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
- ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
-// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
-// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
-// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00004000,
- ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000,
- ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
- ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
- ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- /* Verified against board configuration registers after normal proprietary BIOS boot */
- //ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001033,
- ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000033,
- ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
- ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
- ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration region i
- */
- /* Verified against board configuration registers after normal proprietary BIOS boot */
- ADDRMAP_REG(0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */
- ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
- ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
- ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
-
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
deleted file mode 100644
index 4658d75427..0000000000
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <device/pnp_ops.h>
-#include <device/pci_ops.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <timestamp.h>
-#include <spd.h>
-#include <cpu/amd/model_10xxx_rev.h>
-#include <delay.h>
-#include <cpu/amd/car.h>
-#include <cpu/amd/msr.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627ehg/w83627ehg.h>
-#include <cpu/x86/bist.h>
-#include <northbridge/amd/amdfam10/raminit.h>
-#include <northbridge/amd/amdht/ht_wrapper.h>
-#include <cpu/amd/family_10h-family_15h/init_cpus.h>
-#include <arch/early_variables.h>
-#include <cbmem.h>
-#include <southbridge/amd/common/reset.h>
-#include <southbridge/nvidia/mcp55/mcp55.h>
-
-#include "cpu/amd/quadcore/quadcore.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-
-int spd_read_byte(unsigned int device, unsigned int address);
-
-
-inline int spd_read_byte(unsigned int device, unsigned int address)
-{
- return smbus_read_byte(device, address);
-}
-
-unsigned int get_sbdn(unsigned int bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
-#define MCP55_MB_SETUP \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
-
-#include <southbridge/nvidia/mcp55/early_setup_ss.h>
-#include "southbridge/nvidia/mcp55/early_setup_car.c"
-
-static void sio_setup(void)
-{
- u32 dword;
- u8 byte;
-
- byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0);
- dword |= (1 << 0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0, dword);
-}
-
-static const u8 spd_addr[] = {
- //first node
- RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
- //second node
- RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
-#endif
-};
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- struct sys_info *sysinfo = get_sysinfo();
- u32 bsp_apicid = 0, val, wants_reset;
- u8 reg;
- msr_t msr;
-
- timestamp_init(timestamp_get());
- timestamp_add_now(TS_START_ROMSTAGE);
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- set_bsp_node_CHtExtNodeCfgEn();
- enumerate_ht_chain();
- sio_setup();
- }
-
- post_code(0x30);
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- post_code(0x32);
-
- pnp_enter_conf_state(SERIAL_DEV);
- /* We have 24MHz input. */
- reg = pnp_read_config(SERIAL_DEV, 0x24);
- pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf));
- pnp_exit_conf_state(SERIAL_DEV);
-
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- /* Setup sysinfo defaults */
- set_sysinfo_in_ram(0);
-
- update_microcode(val);
-
- post_code(0x33);
-
- cpuSetAMDMSR(0);
- post_code(0x34);
-
- amd_ht_init(sysinfo);
- post_code(0x35);
-
- /* Setup nodes PCI space and start core 0 AP init. */
- finalize_node_setup(sysinfo);
- printk(BIOS_DEBUG, "finalize_node_setup done\n");
-
- /* Setup any mainboard PCI settings etc. */
- printk(BIOS_DEBUG, "setup_mb_resource_map begin\n");
- setup_mb_resource_map();
- printk(BIOS_DEBUG, "setup_mb_resource_map end\n");
- post_code(0x36);
-
- /* wait for all the APs core0 started by finalize_node_setup. */
- /* FIXME: A bunch of cores are going to start output to serial at once.
- * It would be nice to fixup prink spinlocks for ROM XIP mode.
- * I think it could be done by putting the spinlock flag in the cache
- * of the BSP located right after sysinfo.
- */
- wait_all_core0_started();
-
-#if CONFIG(LOGICAL_CPUS)
- /* Core0 on each node is configured. Now setup any additional cores. */
- printk(BIOS_DEBUG, "start_other_cores()\n");
- start_other_cores(bsp_apicid);
- post_code(0x37);
- printk(BIOS_DEBUG, "wait_all_other_cores_started()\n");
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- post_code(0x38);
-
-#if CONFIG(SET_FIDVID)
- msr = rdmsr(MSR_COFVID_STS);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
-
- /* FIXME: The sb fid change may survive the warm reset and only
- * need to be done once.*/
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
- post_code(0x39);
-
- if (!warm_reset_detect(0)) { // BSP is node 0
- init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
- } else {
- init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
- }
-
- post_code(0x3A);
-
- /* show final fid and vid */
- msr = rdmsr(MSR_COFVID_STS);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
-#endif
- init_timer(); /* Need to use TMICT to synchronize FID/VID. */
-
- wants_reset = mcp55_early_setup_x();
-
- /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
- if (!warm_reset_detect(0)) {
- printk(BIOS_INFO, "...WARM RESET...\n\n\n");
- soft_reset();
- die("After soft_reset - shouldn't see this message!!!\n");
- }
-
- if (wants_reset)
- printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
-
- post_code(0x3B);
-
- /* It's the time to set ctrl in sysinfo now; */
- printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
- post_code(0x3D);
-
- printk(BIOS_DEBUG, "enable_smbus()\n");
- enable_smbus();
-
- post_code(0x40);
-
- raminit_amdmct(sysinfo);
-
- cbmem_initialize_empty();
- post_code(0x41);
-
- amdmct_cbmem_store_info(sysinfo);
-}
-
-/**
- * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
- * Description:
- * This routine is called every time a non-coherent chain is processed.
- * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
- * swap list. The first part of the list controls the BUID assignment and the
- * second part of the list provides the device to device linking. Device orientation
- * can be detected automatically, or explicitly. See documentation for more details.
- *
- * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
- * based on each device's unit count.
- *
- * Parameters:
- * @param[in] node = The node on which this chain is located
- * @param[in] link = The link on the host for this chain
- * @param[out] List = supply a pointer to a list
- */
-BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
-{
- static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
- /* If the BUID was adjusted in early_ht we need to do the manual override */
- if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
- printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
- if ((node == 0) && (link == 0)) { /* BSP SB link */
- *List = swaplist;
- return 1;
- }
- }
-
- return 0;
-}
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