Kill remaining unneeded CAR/ROMCC if-blocks.

Lots of Config.lb files still have "if USE_DCACHE_RAM" sections although
USE_DCACHE_RAM is always set for them. Such checks are not only
pointless, they actively make the files hard to read.

A full abuild run confirmed that compilation did not change with this
patch applied.

The patch does not change whitespace of the remaining code to ease
review and svn blame.

With this change, it should be possible to have two or three Config.lb
variants in total (except the actual hardware config). Right now, some
Config.lb have comments, some don't, some have empty lines for better
readability, some don't, some have leading whitespace, some don't. This
is an utter mess and unifying these files would certainly reduce the
headaches I have when looking at them.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 0 insertions, 44 deletions

diff --git a/src/mainboard/msi/ms7135/Config.lb b/src/mainboard/msi/ms7135/Config.lb
index 1feec7fb63..a0174451cf 100644
--- a/src/mainboard/msi/ms7135/Config.lb
+++ b/src/mainboard/msi/ms7135/Config.lb
@@ -90,7 +90,6 @@ if HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 
-if USE_DCACHE_RAM
 	if CONFIG_USE_INIT
 		makerule ./auto.o
 			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -104,7 +103,6 @@ if USE_DCACHE_RAM
 			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 		end
 	end
-end
 
 ##
 ## Build our 16 bit and 32 bit coreboot entry code.
@@ -123,12 +121,10 @@ end
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
 	if CONFIG_USE_INIT
 		ldscript /cpu/x86/32bit/entry32.lds
 		ldscript /cpu/amd/car/cache_as_ram.lds
 	end
-end
 
 ##
 ## Build our reset vector (this is where coreboot is entered).
@@ -151,12 +147,6 @@ else
 	end
 end
 
-if USE_DCACHE_RAM
-else
-	### Should this be in the northbridge code?
-	mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an ID string (for safe flashing).
 ##
@@ -178,13 +168,10 @@ else
 	end
 end
 
-if USE_DCACHE_RAM
 	##
 	## Setup Cache-As-Ram
 	##
 	mainboardinit cpu/amd/car/cache_as_ram.inc
-end
-
 
 ###
 ### This is the early phase of coreboot startup.
@@ -193,15 +180,11 @@ end
 ###
 if HAVE_FAILOVER_BOOT
 	if USE_FAILOVER_IMAGE
-		if USE_DCACHE_RAM
 			ldscript /arch/i386/lib/failover_failover.lds
-		end
 	end
 else
 	if USE_FALLBACK_IMAGE
-		if USE_DCACHE_RAM
 			ldscript /arch/i386/lib/failover.lds
-		end
 	end
 end
 
@@ -212,13 +195,11 @@ end
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
 	if CONFIG_USE_INIT
 		initobject auto.o
 	else
 		mainboardinit ./auto.inc
 	end
-end
 
 ##
 ## Include the secondary configuration files
diff --git a/src/mainboard/msi/ms7260/Config.lb b/src/mainboard/msi/ms7260/Config.lb
index 992a424208..bdb9933d0a 100644
--- a/src/mainboard/msi/ms7260/Config.lb
+++ b/src/mainboard/msi/ms7260/Config.lb
@@ -54,7 +54,6 @@ if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 # object reset.o
 
-if USE_DCACHE_RAM
   if CONFIG_USE_INIT
     makerule ./cache_as_ram_auto.o
       depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -68,7 +67,6 @@ if USE_DCACHE_RAM
       action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
     end
   end
-end
 
 if USE_FAILOVER_IMAGE
 else
@@ -95,14 +93,12 @@ end
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
   if CONFIG_USE_INIT
     ldscript /cpu/x86/32bit/entry32.lds
   end
   if CONFIG_USE_INIT
     ldscript /cpu/amd/car/cache_as_ram.lds
   end
-end
 
 if HAVE_FAILOVER_BOOT
   if USE_FAILOVER_IMAGE
@@ -138,31 +134,23 @@ else
   end
 end
 
-if USE_DCACHE_RAM
   mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 if HAVE_FAILOVER_BOOT
   if USE_FAILOVER_IMAGE
-    if USE_DCACHE_RAM
       ldscript /arch/i386/lib/failover_failover.lds
-    end
   end
 else
   if USE_FALLBACK_IMAGE
-    if USE_DCACHE_RAM
       ldscript /arch/i386/lib/failover.lds
-    end
   end
 end
 
-if USE_DCACHE_RAM
   if CONFIG_USE_INIT
     initobject cache_as_ram_auto.o
   else
     mainboardinit ./cache_as_ram_auto.inc
   end
-end
 
 config chip.h
 
diff --git a/src/mainboard/msi/ms9185/Config.lb b/src/mainboard/msi/ms9185/Config.lb
index 99f8b77907..99a6ce5e97 100644
--- a/src/mainboard/msi/ms9185/Config.lb
+++ b/src/mainboard/msi/ms9185/Config.lb
@@ -77,8 +77,6 @@ if HAVE_PIRQ_TABLE
        object irq_tables.o
 end
 
-if USE_DCACHE_RAM
-
        if CONFIG_USE_INIT
                # compile cache_as_ram.c to auto.o
                makerule ./cache_as_ram_auto.o
@@ -96,7 +94,6 @@ if USE_DCACHE_RAM
                end
 
        end
-end
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -107,7 +104,6 @@ if USE_FALLBACK_IMAGE
 end
 
 mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -115,7 +111,6 @@ if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -134,12 +129,10 @@ end
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
        ##
        ## Setup Cache-As-Ram
        ##
        mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup
@@ -147,9 +140,7 @@ end
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-       if USE_DCACHE_RAM
                ldscript /arch/i386/lib/failover.lds
-       end
 end
 
 ###
@@ -159,16 +150,12 @@ end
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
        if CONFIG_USE_INIT
                initobject cache_as_ram_auto.o
        else
                mainboardinit ./cache_as_ram_auto.inc
        end
 
-end
-
 ##
 ## Include the secondary Configuration files
 ##