newconfig is no more.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

16 files changed, 0 insertions, 3160 deletions

diff --git a/src/mainboard/msi/ms6119/Config.lb b/src/mainboard/msi/ms6119/Config.lb
deleted file mode 100644
index 79bc904d64..0000000000
--- a/src/mainboard/msi/ms6119/Config.lb
+++ /dev/null
@@ -1,133 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 7.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 3
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.7 on		# GPIO 1
-          end
-          device pnp 3f0.8 on		# GPIO 2
-          end
-          device pnp 3f0.9 on		# GPIO 3
-          end
-          device pnp 3f0.a on		# ACPI
-          end
-        end
-      end
-      device pci 7.1 on	end		# IDE
-      device pci 7.2 on	end		# USB
-      device pci 7.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/msi/ms6119/Options.lb b/src/mainboard/msi/ms6119/Options.lb
deleted file mode 100644
index 7930819f12..0000000000
--- a/src/mainboard/msi/ms6119/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/msi/ms6147/Config.lb b/src/mainboard/msi/ms6147/Config.lb
deleted file mode 100644
index 73f79cbef1..0000000000
--- a/src/mainboard/msi/ms6147/Config.lb
+++ /dev/null
@@ -1,141 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Mats Erik Andersson <mats.andersson@gisladisker.org>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 7.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 3
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.7 on		# GPIO 1
-          end
-          device pnp 3f0.8 on		# GPIO 2
-          end
-          device pnp 3f0.9 off		# GPIO 3
-          end
-          device pnp 3f0.a on		# ACPI
-          end
-        end
-      end
-      device pci 7.1 on end		# IDE
-      device pci 7.2 on end		# USB
-      device pci 7.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "1"
-      register "ide0_drive1_udma33_enable" = "1"
-      register "ide1_drive0_udma33_enable" = "1"
-      register "ide1_drive1_udma33_enable" = "1"
-    end
-  end
-end
diff --git a/src/mainboard/msi/ms6147/Options.lb b/src/mainboard/msi/ms6147/Options.lb
deleted file mode 100644
index e6ccb87bd8..0000000000
--- a/src/mainboard/msi/ms6147/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Mats Erik Andersson <mats.andersson@gisladisker.org>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 8		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/msi/ms6156/Config.lb b/src/mainboard/msi/ms6156/Config.lb
deleted file mode 100644
index 0a93cc772e..0000000000
--- a/src/mainboard/msi/ms6156/Config.lb
+++ /dev/null
@@ -1,134 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 7.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 3
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.7 off		# GPIO 1
-          end
-          device pnp 3f0.8 off		# GPIO 2
-          end
-          device pnp 3f0.9 off		# GPIO 3
-          end
-          device pnp 3f0.a off		# ACPI
-          end
-        end
-      end
-      device pci 7.1 on end		# IDE
-      device pci 7.2 on end		# USB
-      device pci 7.3 on end		# ACPI
-      device pci 14.0 on end		# Onboard audio (Ensoniq ES1371)
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "1"
-      register "ide0_drive1_udma33_enable" = "1"
-      register "ide1_drive0_udma33_enable" = "1"
-      register "ide1_drive1_udma33_enable" = "1"
-    end
-  end
-end
diff --git a/src/mainboard/msi/ms6156/Options.lb b/src/mainboard/msi/ms6156/Options.lb
deleted file mode 100644
index 8d6de68a61..0000000000
--- a/src/mainboard/msi/ms6156/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7
-default CONFIG_MAINBOARD_VENDOR = "MSI"
-default CONFIG_MAINBOARD_PART_NUMBER = "MS-6156"
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/msi/ms6178/Config.lb b/src/mainboard/msi/ms6178/Config.lb
deleted file mode 100644
index 3f77f30555..0000000000
--- a/src/mainboard/msi/ms6178/Config.lb
+++ /dev/null
@@ -1,133 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i82810			# Northbridge
-  device apic_cluster 0 on			# APIC cluster
-    chip cpu/intel/socket_PGA370		# CPU
-      device apic 0 on end			# APIC
-    end
-  end
-  device pci_domain 0 on
-    device pci 0.0 on end			# Host bridge
-    device pci 1.0 on end			# Onboard VGA
-    chip southbridge/intel/i82801xx		# Southbridge
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-
-      device pci 1e.0 on end			# PCI bridge
-      device pci 1f.0 on			# ISA/LPC bridge
-        chip superio/winbond/w83627hf		# Super I/O
-          device pnp 2e.0 on			# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.1 on			# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 3
-          end
-          device pnp 2e.2 on			# Com1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.3 on			# Com2 (only header on board)
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.5 on			# PS/2 keyboard/mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1			# Keyboard interrupt
-            irq 0x72 = 12			# Mouse interrupt
-          end
-          device pnp 2e.6 off end		# Consumer IR (TODO)
-          device pnp 2e.7 on			# Game port / MIDI / GPIO 1
-            io 0x60 = 0x201
-            io 0x62 = 0x330
-            irq 0x70 = 9
-          end
-          device pnp 2e.8 on end		# GPIO 2
-          device pnp 2e.9 on end		# GPIO 3
-          device pnp 2e.a on end		# ACPI
-          device pnp 2e.b on			# Hardware monitor
-            io 0x60 = 0x290
-            irq 0x70 = 5
-          end
-        end
-      end
-      device pci 1f.1 on end			# IDE
-      device pci 1f.2 on end			# USB
-      device pci 1f.3 on end			# SMBus
-      device pci 1f.5 on end			# AC'97 audio
-      device pci 1f.6 on end			# AC'97 modem
-    end
-  end
-end
-
diff --git a/src/mainboard/msi/ms6178/Options.lb b/src/mainboard/msi/ms6178/Options.lb
deleted file mode 100644
index 04660f0c55..0000000000
--- a/src/mainboard/msi/ms6178/Options.lb
+++ /dev/null
@@ -1,99 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_WRITE_HIGH_TABLES
-uses CONFIG_VIDEO_MB
-
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 4		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-default CONFIG_WRITE_HIGH_TABLES = 1
-default CONFIG_VIDEO_MB = 1
-end
diff --git a/src/mainboard/msi/ms7135/Config.lb b/src/mainboard/msi/ms7135/Config.lb
deleted file mode 100644
index adc58a9a11..0000000000
--- a/src/mainboard/msi/ms7135/Config.lb
+++ /dev/null
@@ -1,241 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
-## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
-## (Thanks to LSRA University of Mannheim for their support)
-## Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/ati/ragexl
-
-# Needed by irq_tables and mptable and acpi_tables.
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE
-	object mptable.o
-end
-
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-
-	if CONFIG_USE_INIT
-		makerule ./auto.o
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-	else
-		makerule ./auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code.
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-	if CONFIG_USE_FAILOVER_IMAGE
-		mainboardinit cpu/x86/16bit/entry16.inc
-		ldscript /cpu/x86/16bit/entry16.lds
-	end
-else
-	if CONFIG_USE_FALLBACK_IMAGE
-		mainboardinit cpu/x86/16bit/entry16.inc
-		ldscript /cpu/x86/16bit/entry16.lds
-	end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-	if CONFIG_USE_INIT
-		ldscript /cpu/x86/32bit/entry32.lds
-		ldscript /cpu/amd/car/cache_as_ram.lds
-	end
-
-##
-## Build our reset vector (this is where coreboot is entered).
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-	if CONFIG_USE_FAILOVER_IMAGE
-		mainboardinit cpu/x86/16bit/reset16.inc
-		ldscript /cpu/x86/16bit/reset16.lds
-	else
-		mainboardinit cpu/x86/32bit/reset32.inc
-		ldscript /cpu/x86/32bit/reset32.lds
-	end
-else
-	if CONFIG_USE_FALLBACK_IMAGE
-		mainboardinit cpu/x86/16bit/reset16.inc
-		ldscript /cpu/x86/16bit/reset16.lds
-	else
-		mainboardinit cpu/x86/32bit/reset32.inc
-		ldscript /cpu/x86/32bit/reset32.lds
-	end
-end
-
-##
-## Include an ID string (for safe flashing).
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## ROMSTRAP table for CK804
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-	if CONFIG_USE_FAILOVER_IMAGE
-		mainboardinit southbridge/nvidia/ck804/romstrap.inc
-		ldscript /southbridge/nvidia/ck804/romstrap.lds
-	end
-else
-	if CONFIG_USE_FALLBACK_IMAGE
-		mainboardinit southbridge/nvidia/ck804/romstrap.inc
-		ldscript /southbridge/nvidia/ck804/romstrap.lds
-	end
-end
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup.
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_HAVE_FAILOVER_BOOT
-	if CONFIG_USE_FAILOVER_IMAGE
-			ldscript /arch/i386/lib/failover_failover.lds
-	end
-else
-	if CONFIG_USE_FALLBACK_IMAGE
-			ldscript /arch/i386/lib/failover.lds
-	end
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject auto.o
-	else
-		mainboardinit ./auto.inc
-	end
-
-##
-## Include the secondary configuration files
-##
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex		# Root complex
-  device apic_cluster 0 on			# APIC cluster
-    chip cpu/amd/socket_754			# Socket 754 CPU
-      device apic 0 on end			# APIC
-    end
-  end
-
-  device pci_domain 0 on			# PCI domain
-    chip northbridge/amd/amdk8			# mc0
-      device pci 18.0 on			# Northbridge
-        # Devices on link 0, link 0 == LDT 0
-        chip southbridge/nvidia/ck804		# Southbridge
-          device pci 0.0 on end			# HT
-          device pci 1.0 on			# LPC
-            chip superio/winbond/w83627thf	# Super I/O
-              device pnp 4e.0 on		# Floppy
-                io 0x60 = 0x3f0
-                irq 0x70 = 6
-                drq 0x74 = 2
-              end
-              device pnp 4e.1 on		# Parallel port
-                io 0x60 = 0x378
-                irq 0x70 = 7
-              end
-              device pnp 4e.2 on		# Com1
-                io 0x60 = 0x3f8
-                irq 0x70 = 4
-              end
-              device pnp 4e.3 on		# Com2
-                io 0x60 = 0x2f8
-                irq 0x70 = 3
-              end
-              device pnp 4e.5 on		# PS/2 keyboard
-                io 0x60 = 0x60
-                io 0x62 = 0x64
-                irq 0x70 = 1
-                irq 0x72 = 12
-              end
-              device pnp 4e.7 off end		# Game, MIDI, GPIO 1, GPIO 5
-              device pnp 4e.8 off end		# GPIO 2
-              device pnp 4e.9 off end		# GPIO 3, GPIO 4
-              device pnp 4e.a off end		# ACPI
-              device pnp 4e.b on		# Hardware monitor
-                io 0x60 = 0x290
-                irq 0x70 = 0
-              end
-            end
-          end
-          device pci 1.1 on end			# SMbus
-          device pci 2.0 on end			# USB 1.1
-          device pci 2.1 on end			# USB 2
-          device pci 4.0 on end			# Onboard audio (ACI)
-          device pci 4.1 off end		# Onboard modem (MCI) -- not wired out
-          device pci 6.0 on end			# IDE
-          device pci 7.0 on end			# SATA 1
-          device pci 8.0 on end			# SATA 0
-          device pci 9.0 on end			# PCI
-          device pci a.0 on end			# NIC
-          device pci b.0 off end		# PCI E 3 -- not wired out
-          device pci c.0 off end		# PCI E 2 -- not wired out
-          device pci d.0 on end			# PCI E 1
-          device pci e.0 on end			# PCI E 0
-          register "ide0_enable" = "1"
-          register "ide1_enable" = "1"
-          register "sata0_enable" = "1"
-          register "sata1_enable" = "1"
-          # register "mac_eeprom_smbus" = "3"
-          # register "mac_eeprom_addr" = "0x51"
-        end
-      end
-      device pci 18.1 on end
-      device pci 18.2 on end
-      device pci 18.3 on end
-    end
-  end
-end
diff --git a/src/mainboard/msi/ms7135/Options.lb b/src/mainboard/msi/ms7135/Options.lb
deleted file mode 100644
index b3b2b4beaf..0000000000
--- a/src/mainboard/msi/ms7135/Options.lb
+++ /dev/null
@@ -1,321 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
-## (Thanks to LSRA University of Mannheim for their support)
-## Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_CONSOLE_BTEXT
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_AP_CODE_IN_CAR
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_MEM_TRAIN_SEQ
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_ID_SECTION_OFFSET
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-## ---> 512 Kbytes 
-default CONFIG_ROM_SIZE=(512*1024)
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-#FAILOVER: 4K
-default CONFIG_FAILOVER_SIZE=(4*1024)
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_HAVE_FAILOVER_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=13
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-default CONFIG_MAX_PHYSICAL_CPUS=1
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-##HT Unit ID offset, default is 1, the typical one
-default CONFIG_HT_CHAIN_UNITID_BASE=0
-
-##real SB Unit ID, default is 0x20, mean dont touch it at last
-#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x10
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-##only offset for SB chain?, default is yes(1)
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#BTEXT Console
-#default CONFIG_CONSOLE_BTEXT=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-#default CONFIG_DCACHE_RAM_BASE=0xcf000
-#default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x08000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-default CONFIG_AP_CODE_IN_CAR=0
-default CONFIG_MEM_TRAIN_SEQ=2
-default CONFIG_WAIT_BEFORE_CPUS_INIT=0
-
-## APIC stuff
-#default CONFIG_ENABLE_APIC_EXT_ID=0
-#default CONFIG_APIC_ID_OFFSET=0x10
-#default CONFIG_LIFT_BSP_APIC_ID=0
-
-
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="K8N Neo3 (MS-7135)"
-default CONFIG_MAINBOARD_VENDOR="MSI"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x7135
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = (64*1024) - CONFIG_FAILOVER_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#efault CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
-
-##
-## coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_ID_SECTION_OFFSET=0x80
-
-### End Options.lb
-end
diff --git a/src/mainboard/msi/ms7260/Config.lb b/src/mainboard/msi/ms7260/Config.lb
deleted file mode 100644
index f420731f42..0000000000
--- a/src/mainboard/msi/ms7260/Config.lb
+++ /dev/null
@@ -1,288 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end
-
-driver mainboard.o
-object get_bus_conf.o # Needed by irq_tables and mptable (and acpi_tables).
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-  if CONFIG_USE_INIT
-    makerule ./cache_as_ram_auto.o
-      depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-    end
-  else
-    makerule ./cache_as_ram_auto.inc
-      depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-      action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-      action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-    end
-  end
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-  if CONFIG_AP_CODE_IN_CAR
-    makerule ./apc_auto.o
-      depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
-      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
-    end
-    ldscript /arch/i386/init/ldscript_apc.lb
-  end
-end
-
-if CONFIG_HAVE_FAILOVER_BOOT
-  if CONFIG_USE_FAILOVER_IMAGE
-    mainboardinit cpu/x86/16bit/entry16.inc
-    ldscript /cpu/x86/16bit/entry16.lds
-  end
-else
-  if CONFIG_USE_FALLBACK_IMAGE
-    mainboardinit cpu/x86/16bit/entry16.inc
-    ldscript /cpu/x86/16bit/entry16.lds
-  end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-  if CONFIG_USE_INIT
-    ldscript /cpu/x86/32bit/entry32.lds
-  end
-  if CONFIG_USE_INIT
-    ldscript /cpu/amd/car/cache_as_ram.lds
-  end
-
-if CONFIG_HAVE_FAILOVER_BOOT
-  if CONFIG_USE_FAILOVER_IMAGE
-    mainboardinit cpu/x86/16bit/reset16.inc
-    ldscript /cpu/x86/16bit/reset16.lds
-  else
-    mainboardinit cpu/x86/32bit/reset32.inc
-    ldscript /cpu/x86/32bit/reset32.lds
-  end
-else
-  if CONFIG_USE_FALLBACK_IMAGE
-    mainboardinit cpu/x86/16bit/reset16.inc
-    ldscript /cpu/x86/16bit/reset16.lds
-  else
-    mainboardinit cpu/x86/32bit/reset32.inc
-    ldscript /cpu/x86/32bit/reset32.lds
-  end
-end
-
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-# ROMSTRAP table for MCP55.
-if CONFIG_HAVE_FAILOVER_BOOT
-  if CONFIG_USE_FAILOVER_IMAGE
-    mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-    ldscript /southbridge/nvidia/mcp55/romstrap.lds
-  end
-else
-  if CONFIG_USE_FALLBACK_IMAGE
-    mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-    ldscript /southbridge/nvidia/mcp55/romstrap.lds
-  end
-end
-
-  mainboardinit cpu/amd/car/cache_as_ram.inc
-
-if CONFIG_HAVE_FAILOVER_BOOT
-  if CONFIG_USE_FAILOVER_IMAGE
-      ldscript /arch/i386/lib/failover_failover.lds
-  end
-else
-  if CONFIG_USE_FALLBACK_IMAGE
-      ldscript /arch/i386/lib/failover.lds
-  end
-end
-
-  if CONFIG_USE_INIT
-    initobject cache_as_ram_auto.o
-  else
-    mainboardinit ./cache_as_ram_auto.inc
-  end
-
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex		# Root complex
-  device apic_cluster 0 on			# APIC cluster
-    chip cpu/amd/socket_AM2			# CPU
-      device apic 0 on end			# APIC
-    end
-  end
-  device pci_domain 0 on			# PCI domain
-    chip northbridge/amd/amdk8			# Northbridge / mc0
-      device pci 18.0 on
-        # Devices on link 0, link 0 == LDT 0
-        chip southbridge/nvidia/mcp55		# Southbridge
-          device pci 0.0 on end			# HT
-          device pci 1.0 on			# LPC
-            chip superio/winbond/w83627ehg	# Super I/O
-              device pnp 4e.0 on		# Floppy
-                io 0x60 = 0x3f0
-                irq 0x70 = 6
-                drq 0x74 = 2
-              end
-              device pnp 4e.1 on		# Parallel port
-                io 0x60 = 0x378
-                irq 0x70 = 7
-              end
-              device pnp 4e.2 on		# Com1
-                io 0x60 = 0x3f8
-                irq 0x70 = 4
-              end
-              device pnp 4e.3 on		# Com2 / IrDA
-                io 0x60 = 0x2f8
-                irq 0x70 = 3
-              end
-              device pnp 4e.5 on		# PS/2 keyboard
-                io 0x60 = 0x60
-                io 0x62 = 0x64
-                irq 0x70 = 1			# PS/2 keyboard IRQ
-                irq 0x72 = 12			# PS/2 mouse IRQ
-              end
-              device pnp 4e.6 off		# Serial flash interface
-                # io 0x62 = 0x100
-              end
-              device pnp 4e.7 off		# GPIO1/6, game port, MIDI port
-                # io 0x60 = 0x220		# Datasheet: 0x201
-                # io 0x62 = 0x300		# Datasheet: 0x330
-                # irq 0x70 = 9
-              end
-              device pnp 4e.8 off		# WDTO#, PLED
-              end
-              device pnp 4e.9 off		# GPIO2/3/4/5, SUSLED
-              end
-              device pnp 4e.a off		# ACPI
-              end
-              device pnp 4e.b on		# HWM (for lm-sensors)
-                io 0x60 = 0xa10
-              end
-            end
-          end
-          device pci 1.1 on			# SM 0
-            chip drivers/generic/generic	# DIMM 0-0-0
-              device i2c 50 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-0-1
-              device i2c 51 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-1-0
-              device i2c 52 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-1-1
-              device i2c 53 on end
-            end
-            # TODO: Needed?
-            # chip drivers/generic/generic	# DIMM 1-0-0
-            #   device i2c 54 on end
-            # end
-            # chip drivers/generic/generic	# DIMM 1-0-1
-            #   device i2c 55 on end
-            # end
-            # chip drivers/generic/generic	# DIMM 1-1-0
-            #   device i2c 56 on end
-            # end
-            # chip drivers/generic/generic	# DIMM 1-1-1
-            #   device i2c 57 on end
-            # end
-          end
-          # TODO: Check if the stuff below is correct / needed.
-          device pci 1.1 on			# SM 1
-            # PCI device SMBus address will depend on addon PCI device,
-            # do we need to scan_smbus_bus?
-
-            # chip drivers/generic/generic	# PCIXA Slot1
-            #   device i2c 50 on end
-            # end
-            # chip drivers/generic/generic	# PCIXB Slot1
-            #   device i2c 51 on end
-            # end
-            # chip drivers/generic/generic	# PCIXB Slot2
-            #   device i2c 52 on end
-            # end
-            # chip drivers/generic/generic	# PCI Slot1
-            #   device i2c 53 on end
-            # end
-            # chip drivers/generic/generic	# Master MCP55 PCI-E
-            #   device i2c 54 on end
-            # end
-            # chip drivers/generic/generic	# Slave MCP55 PCI-E
-            #   device i2c 55 on end
-            # end
-            chip drivers/generic/generic	# MAC EEPROM
-              device i2c 51 on end
-            end
-          end
-          device pci 2.0 on end			# USB 1.1
-          device pci 2.1 on end			# USB 2
-          device pci 4.0 on end			# IDE
-          device pci 5.0 on end			# SATA 0
-          device pci 5.1 on end			# SATA 1
-          device pci 5.2 off end		# SATA 2 (N/A on this board)
-          device pci 6.0 on end			# PCI
-          device pci 6.1 on end			# AZA (HD Audio)
-          device pci 8.0 on end			# NIC
-          device pci 9.0 off end		# NIC (N/A on this board)
-          device pci a.0 off end		# PCI E 5 (N/A on this board?)
-          device pci b.0 on end			# PCI E 4
-          device pci c.0 on end			# PCI E 3
-          device pci d.0 on end			# PCI E 2
-          device pci e.0 on end			# PCI E 1
-          device pci f.0 on end			# PCI E 0
-          register "ide0_enable" = "1"
-          register "sata0_enable" = "1"
-          register "sata1_enable" = "1"
-          # TODO: Check the two lines below.
-          register "mac_eeprom_smbus" = "3"	# 1: SMBus under 2e.8, 2: SM0 3: SM1
-          register "mac_eeprom_addr" = "0x51"
-        end
-      end
-      device pci 18.0 on end			# Link 1
-      device pci 18.0 on end
-      device pci 18.1 on end
-      device pci 18.2 on end
-      device pci 18.3 on end
-    end
-  end
-
-# TODO
-#  chip drivers/generic/debug
-#    device pnp 0.0 off end			# chip name
-#    device pnp 0.1 on end			# pci_regs_all
-#    device pnp 0.2 on end			# mem
-#    device pnp 0.3 off end			# cpuid
-#    device pnp 0.4 on end			# smbus_regs_all
-#    device pnp 0.5 off end			# dual core msr
-#    device pnp 0.6 off end			# cache size
-#    device pnp 0.7 off end			# tsc
-#    device pnp 0.8 off end			# io
-#    device pnp 0.9 off end			# io
-#  end
-
-end
diff --git a/src/mainboard/msi/ms7260/Options.lb b/src/mainboard/msi/ms7260/Options.lb
deleted file mode 100644
index 1be372ae6c..0000000000
--- a/src/mainboard/msi/ms7260/Options.lb
+++ /dev/null
@@ -1,188 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER			# ?
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_USBDEBUG_DIRECT
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_SERIAL_CPU_INIT
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-uses CONFIG_PCI_64BIT_PREF_MEM
-uses CONFIG_RAMTOP
-uses CONFIG_AP_CODE_IN_CAR
-uses CONFIG_MEM_TRAIN_SEQ
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_ID_SECTION_OFFSET
-
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_FAILOVER_SIZE = 4 * 1024
-default CONFIG_RAMTOP = 2048*1024	# 1MB more for pgtbl.
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_HAVE_FAILOVER_BOOT = 1
-default CONFIG_HAVE_HARD_RESET = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 11		# TODO: Check if correct.
-default CONFIG_GENERATE_MP_TABLE = 1		# TODO: Check if correct.
-default CONFIG_HAVE_OPTION_TABLE = 1
-default CONFIG_SMP = 1
-default CONFIG_MAX_CPUS = 2
-default CONFIG_MAX_PHYSICAL_CPUS = 1
-default CONFIG_LOGICAL_CPUS = 1
-# default CONFIG_SERIAL_CPU_INIT = 0
-default CONFIG_ENABLE_APIC_EXT_ID = 0
-default CONFIG_APIC_ID_OFFSET = 0x10
-default CONFIG_LIFT_BSP_APIC_ID = 1
-
-# Move the default coreboot CMOS range off of AMD RTC registers.
-default CONFIG_LB_CKS_RANGE_START = 49
-default CONFIG_LB_CKS_RANGE_END = 122
-default CONFIG_LB_CKS_LOC = 123
-
-# Memory hole size. 0 means disable, others will enable the hole. In that
-# case, if it is smaller than mmio_basek, it will use mmio_basek instead.
-# default CONFIG_HW_MEM_HOLE_SIZEK = 0x200000	# 2GB
-default CONFIG_HW_MEM_HOLE_SIZEK = 0x100000	# 1GB
-# default CONFIG_HW_MEM_HOLE_SIZEK = 0x80000	# 512MB
-
-# Make auto increase hole size to avoid hole_startk equal to basek so as
-# to make some kernel happy.
-# default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC = 1
-
-# Opteron K8 1G HT support.
-default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1
-
-# HT Unit ID offset, default is 1, the typical one, 0 means only one HT device.
-default CONFIG_HT_CHAIN_UNITID_BASE = 0
-
-# Real SB Unit ID, default is 0x20, mean don't touch it at last.
-# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-
-# Make the SB HT chain on bus 0, default is not (0).
-default CONFIG_SB_HT_CHAIN_ON_BUS0 = 2
-
-# Only offset for SB chain? Default is yes (1).
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
-
-# Allow capable device use that above 4GB.
-# default CONFIG_PCI_64BIT_PREF_MEM = 1
-
-default CONFIG_CONSOLE_VGA = 1		# Needed for VGA.
-default CONFIG_PCI_ROM_RUN = 1		# Needed for VGA.
-default CONFIG_USBDEBUG_DIRECT = 0
-default CONFIG_USE_DCACHE_RAM = 1
-default CONFIG_DCACHE_RAM_BASE = 0xc8000
-default CONFIG_DCACHE_RAM_SIZE = 0x08000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
-default CONFIG_USE_INIT = 0
-default CONFIG_AP_CODE_IN_CAR = 0
-default CONFIG_MEM_TRAIN_SEQ = 2
-default CONFIG_WAIT_BEFORE_CPUS_INIT = 0
-default CONFIG_IOAPIC = 1
-default CONFIG_MAINBOARD_PART_NUMBER = "K9N Neo (MS-7260)"
-default CONFIG_MAINBOARD_VENDOR = "MSI"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x7260
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
-default CONFIG_STACK_SIZE = 0x2000
-default CONFIG_HEAP_SIZE = 0x8000
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE)
-default CONFIG_RAMBASE = 0x00100000
-default CONFIG_ROM_PAYLOAD = 1
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_USE_PRINTK_IN_CAR = 1
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
-default CONFIG_ID_SECTION_OFFSET=0x80
-
-end
diff --git a/src/mainboard/msi/ms9185/Config.lb b/src/mainboard/msi/ms9185/Config.lb
deleted file mode 100644
index c3bddcfe1f..0000000000
--- a/src/mainboard/msi/ms9185/Config.lb
+++ /dev/null
@@ -1,231 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## Copyright (C) 2006 MSI
-## Written by bxshi <bingxunshi@gmail.com> for MSI.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/si/3114
-
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE
-       object mptable.o
-end
-
-if CONFIG_GENERATE_PIRQ_TABLE
-       object irq_tables.o
-end
-
-       if CONFIG_USE_INIT
-               # compile cache_as_ram.c to auto.o
-               makerule ./cache_as_ram_auto.o
-                       depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-                       action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-               end
-
-       else
-               #compile cache_as_ram.c to auto.inc
-               makerule ./cache_as_ram_auto.inc
-                       depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-                       action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-                       action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-                       action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-               end
-
-       end
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-
-if CONFIG_USE_FALLBACK_IMAGE
-       mainboardinit cpu/x86/16bit/entry16.inc
-       ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-       mainboardinit cpu/x86/16bit/reset16.inc
-       ldscript /cpu/x86/16bit/reset16.lds
-else
-       mainboardinit cpu/x86/32bit/reset32.inc
-       ldscript /cpu/x86/32bit/reset32.lds
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-       ##
-       ## Setup Cache-As-Ram
-       ##
-       mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-               ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-       if CONFIG_USE_INIT
-               initobject cache_as_ram_auto.o
-       else
-               mainboardinit ./cache_as_ram_auto.inc
-       end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-# sample config for amd/serengeti_cheetah
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_F
-                        device apic 0 on end
-                end
-        end
-       device pci_domain 0 on
-               chip northbridge/amd/amdk8
-                       device pci 18.0 on end
-                       device pci 18.0 on end
-                       device pci 18.0 on #  northbridge
-                              #  devices on link 0
-                                chip southbridge/broadcom/bcm5780 # HT2000
-                                        device pci 0.0 on end   # PXB 1 0x0130
-                                        device pci 1.0 on       # PXB 2 0x0130
-                                                device pci 4.0 on end # GB E 0x1668 vid = 0x14e4
-                                                device pci 4.1 on end # GB E 0x1669 vid = 0x14e4
-                                        end
-                                        device pci 2.0 on end # PCI E 1  #0x0132
-                                       device pci 3.0 on end # PCI E 2
-                                       device pci 4.0 on end # PCI E 3
-                                       device pci 5.0 on end # PCI E 4
-                                end
-                                chip southbridge/broadcom/bcm5785 # HT1000
-                                        device pci 0.0 on  # HT PXB  0x0036
-                                                device pci d.0 on end # PPBX 0x0104
-                                                device pci e.0 on end # SATA 0x024a
-                                                device pci e.1 on end # SATA 0x024a bx_a001
-                                                device pci e.2 on end # SATA 0x024a bx_a001
-                                                device pci e.3 on end # SATA 0x024a bx_a001
-                                        end
-                                        device pci 1.0 on # Legacy  pci main  0x0205
-                                       end
-                                        device pci 1.1 on end # IDE        0x0214
-                                        device pci 1.2 on     # LPC        0x0234
-                                                chip superio/nsc/pc87417
-                                                        device  pnp 2e.0 off  # Floppy
-                                                                 io 0x60 = 0x3f0
-                                                                irq 0x70 = 6
-                                                                drq 0x74 = 2
-                                                        end
-                                                        device pnp 2e.1 off  # Parallel Port
-                                                                 io 0x60 = 0x378
-                                                                irq 0x70 = 7
-                                                        end
-                                                        device pnp 2e.2 off # Com 2
-                                                                 io 0x60 = 0x2f8
-                                                                irq 0x70 = 3
-                                                        end
-                                                        device pnp 2e.3 on  # Com 1
-                                                                 io 0x60 = 0x3f8
-                                                                irq 0x70 = 4
-                                                        end
-                                                        device pnp 2e.4 off end # SWC
-                                                        device pnp 2e.5 off end # Mouse
-                                                        device pnp 2e.6 on  # Keyboard
-                                                                 io 0x60 = 0x60
-                                                                 io 0x62 = 0x64
-                                                                irq 0x70 = 1
-                                                        end
-                                                        device pnp 2e.7 off end # GPIO
-                                                        device pnp 2e.f off end # XBUS
-                                                        device pnp 2e.10 on #RTC
-                                                                io 0x60 = 0x70
-                                                                io 0x62 = 0x72
-                                                       end
-                                                end
-                                        end
-                                        device pci 1.3 on end # WDTimer    0x0238
-                                        device pci 1.4 on end # XIOAPIC0   0x0235
-                                        device pci 1.5 on end # XIOAPIC1
-                                        device pci 1.6 on end # XIOAPIC2
-                                        device pci 2.0 on end # USB        0x0223
-                                        device pci 2.1 on end # USB
-                                        device pci 2.2 on end # USB
-                                        device pci 3.0 on end # it is in bcm5785_0 bus
-                                end
-                       end #  device pci 18.0
-                       device pci 18.1 on end
-                       device pci 18.2 on end
-                       device pci 18.3 on end
-               end # amdk8
-       end #pci_domain
-#        chip drivers/generic/debug
-#              device pnp 0.0 off end # chip name
-#                device pnp 0.1 on end # pci_regs_all
-#                device pnp 0.2 off end # mem
-#                device pnp 0.3 off end # cpuid
-#                device pnp 0.4 off end # smbus_regs_all
-#                device pnp 0.5 off end # dual core msr
-#                device pnp 0.6 off end # cache size
-#                device pnp 0.7 off end # tsc
-#       end
-
-end
-
-
diff --git a/src/mainboard/msi/ms9185/Options.lb b/src/mainboard/msi/ms9185/Options.lb
deleted file mode 100644
index d3423f59e1..0000000000
--- a/src/mainboard/msi/ms9185/Options.lb
+++ /dev/null
@@ -1,327 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## Copyright (C) 2006 MSI
-## Written by bxshi <bingxunshi@gmail.com> for MSI.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_ACPI_SSDTX_NUM
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SERIAL_CPU_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_RAMTOP
-uses CONFIG_USE_PRINTK_IN_CAR
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-#more 1M for pgtbl
-default CONFIG_RAMTOP=2048*1024
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-#default CONFIG_GENERATE_ACPI_TABLES=1
-## extra SSDT num
-#default CONFIG_ACPI_SSDTX_NUM=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-default CONFIG_SERIAL_CPU_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=0
-default CONFIG_APIC_ID_OFFSET=0x8
-default CONFIG_LIFT_BSP_APIC_ID=1
-
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
-#2G
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
-#1G
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-#512M
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
-
-#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
-
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-#HT Unit ID offset, default is 1, the typical one
-default CONFIG_HT_CHAIN_UNITID_BASE=0x06
-
-#real SB Unit ID, default is 0x20, mean dont touch it at last
-default CONFIG_HT_CHAIN_END_UNITID_BASE=0x01
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-#only offset for SB chain?, default is yes(1)
-#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#allow capable device use that above 4G
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcc000
-default CONFIG_DCACHE_RAM_SIZE=0x04000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="MS9185"
-default CONFIG_MAINBOARD_VENDOR="MSI"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00100000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/msi/ms9282/Config.lb b/src/mainboard/msi/ms9282/Config.lb
deleted file mode 100644
index ec1211e7b4..0000000000
--- a/src/mainboard/msi/ms9282/Config.lb
+++ /dev/null
@@ -1,322 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## Copyright (C) 2006 MSI
-## Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_ROM_PAYLOAD = 1
-
-arch i386 end
-
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/ati/ragexl
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_USE_INIT
-
-makerule ./auto.o
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-end
-
-else
-
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-       action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-       action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/entry16.inc
-        ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-       if CONFIG_USE_INIT
-               ldscript /cpu/x86/32bit/entry32.lds
-       end
-
-       if CONFIG_USE_INIT
-               ldscript      /cpu/amd/car/cache_as_ram.lds
-       end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-       mainboardinit cpu/x86/16bit/reset16.inc
-       ldscript /cpu/x86/16bit/reset16.lds
-else
-       mainboardinit cpu/x86/32bit/reset32.inc
-       ldscript /cpu/x86/32bit/reset32.lds
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## ROMSTRAP table for MCP55
-##
-if CONFIG_USE_FALLBACK_IMAGE
-       mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-       ldscript /southbridge/nvidia/mcp55/romstrap.lds
-end
-
-##
-## Setup Cache-As-Ram
-##
-mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-       ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-
-# sample config for msi/ms9282
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_F
-                        device apic 0 on end
-                end
-        end
-
-       device pci_domain 0 on
-               chip northbridge/amd/amdk8 #mc0
-                       device pci 18.0 on #  northbridge
-                               #  devices on link 0, link 0 == LDT 0
-                               chip southbridge/nvidia/mcp55
-                                       device pci 0.0 on end   # HT
-                                       device pci 1.0 on # LPC
-                                               chip superio/winbond/w83627ehg
-                                                       device pnp 2e.0 on #  Floppy
-                                                               io 0x60 = 0x3f0
-                                                               irq 0x70 = 6
-                                                               drq 0x74 = 2
-                                                       end
-                                                       device pnp 2e.1 off #  Parallel Port
-                                                               io 0x60 = 0x378
-                                                               irq 0x70 = 7
-                                                       end
-                                                       device pnp 2e.2 on #  Com1
-                                                               io 0x60 = 0x3f8
-                                                               irq 0x70 = 4
-                                                       end
-                                                       device pnp 2e.3 off #  Com2
-                                                               io 0x60 = 0x2f8
-                                                               irq 0x70 = 3
-                                                       end
-                                                       device pnp 2e.5 on #  Keyboard
-                                                               io 0x60 = 0x60
-                                                               io 0x62 = 0x64
-                                                               irq 0x70 = 1
-                                                               irq 0x72 = 12
-                                                       end
-                                                       device pnp 2e.6 off #  SERIAL_FALSH
-                                                               io 0x60 = 0x100
-                                                       end
-                                                       device pnp 2e.7 off #  GAME_MIDI_GIPO1
-                                                               io 0x60 = 0x220
-                                                               io 0x62 = 0x300
-                                                               irq 0x70 = 9
-                                                       end
-                                                       device pnp 2e.8 off end #  WDTO_PLED
-                                                       device pnp 2e.9 off end #  GPIO2_GPIO3_GPIO4_GPIO5
-                                                       device pnp 2e.a off end #  ACPI
-                                                       device pnp 2e.b on #  HW Monitor
-                                                               io 0x60 = 0x290
-                                                               irq 0x70 = 5
-                                                       end
-                                               end
-                                       end
-                                        device pci 1.1 on # SM 0
-                                               chip drivers/i2c/i2cmux2 # pca9554 smbus mux
-                                                       device i2c 70 on  #0 pca9554 1
-                                                               chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 50 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 51 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 52 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 53 on end
-                                                                end
-                                                               chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 54 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 55 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 56 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 57 on end
-                                                                end
-                                                       end
-                                                       device i2c 70 on  #0 pca9554 2
-                                                               chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 50 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 51 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 52 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 53 on end
-                                                                end
-                                                               chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 54 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 55 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 56 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 57 on end
-                                                                end
-                                                       end
-                                               end
-                                       end
-                                       device pci 1.1 on # SM 1
-                                               chip drivers/i2c/i2cmux2 # pca9554 smbus mux
-                                                       device i2c 72 on     #pca9554 channle1
-                                                               chip drivers/i2c/adm1027   #HWM ADT7476 1
-                                                                       device i2c 2e on end
-                                                               end
-                                                       end
-                                                       device i2c 72 on     #pca9545 channel 2
-                                                               chip drivers/i2c/adm1027   #HWM ADT7463
-                                                                       device i2c 2e on end
-                                                               end
-                                                       end
-                                                       device i2c 72 on end  #pca9545 channel 3
-                                                       device i2c 72 on      #pca9545 channel 4
-                                                               chip drivers/i2c/adm1027   #HWM ADT7476 2
-                                                                       device i2c 2e on end
-                                                               end
-                                                       end
-                                               end
-                                       end
-
-                                       device pci 2.0 on end # USB 1.1
-                                       device pci 2.1 on end # USB 2
-                                       device pci 4.0 on  end # IDE
-                                               device pci 5.0 on  end # SATA 0
-                                       device pci 5.1 on  end # SATA 1
-                                       device pci 5.2 on  end # SATA 2
-                                       device pci 6.0 on  #P2P
-                                               device pci 4.0 on end
-                                       end # P2P
-                                       device pci 7.0 on end # reserve
-                                       device pci 8.0 on end # MAC0
-                                       device pci 9.0 on end # MAC1
-                                       device pci a.0 on
-                                               device pci 0.0 on
-                                                       device pci 4.0 on end  #pci_E lan1
-                                                       device pci 4.1 on end  #pci_E lan2
-                                               end
-                                       end # 0x376
-                                               device pci b.0 on  end # PCI E 0x374
-                                       device pci c.0 on  end
-                                       device pci d.0 on   #SAS
-                                               device pci 0.0 on end
-                                       end # PCI E 1 0x378
-                                       device pci e.0 on end # PCI E 0 0x375
-                                       device pci f.0 on end   #PCI E 0x377  pci_E slot
-                                       register "ide0_enable" = "1"
-                                       register "ide1_enable" = "1"
-                                       register "sata0_enable" = "1"
-                                       register "sata1_enable" = "1"
-                               end
-                       end #  device pci 18.0
-                       device pci 18.0 on end # Link 1
-                       device pci 18.0 on end
-                       device pci 18.1 on end
-                       device pci 18.2 on end
-                       device pci 18.3 on end
-               end #mc0
-
-       end # pci_domain
-
-#        chip drivers/generic/debug
-#                device pnp 0.0 off end
-#                device pnp 0.1 off end
-#                device pnp 0.2 off end
-#                device pnp 0.3 off end
-#                device pnp 0.4 off end
-#              device pnp 0.5 on end
-#        end
-end # root_complex
diff --git a/src/mainboard/msi/ms9282/Options.lb b/src/mainboard/msi/ms9282/Options.lb
deleted file mode 100644
index ee8be01679..0000000000
--- a/src/mainboard/msi/ms9282/Options.lb
+++ /dev/null
@@ -1,311 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## Copyright (C) 2006 MSI
-## Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-#bx_b001- uses K8_HW_MEM_HOLE_SIZEK
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-#bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-#bx_b005+
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-
-# stepan 2007-04-12
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_ID_SECTION_OFFSET
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-#512K bytes
-default CONFIG_ROM_SIZE=524288
-
-#1M bytes
-#bx- default CONFIG_ROM_SIZE=1048576
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-#bx_b001- default K8_HW_MEM_HOLE_SIZEK=0x100000
-
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-
-##HT Unit ID offset, default is 1, the typical one
-default CONFIG_HT_CHAIN_UNITID_BASE=0x0
-
-##real SB Unit ID, default is 0x20, mean dont touch it at last
-#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0
-
-#make the SB HT chain on bus 0, default is not (0)
-#bx_b001- default K8_SB_HT_CHAIN_ON_BUS0=2
-
-##bx_b005+ make the SB HT chain on bus 0
-default CONFIG_SB_HT_CHAIN_ON_BUS0=1
-
-##only offset for SB chain?, default is yes(1)
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#VGA
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcc000
-default CONFIG_DCACHE_RAM_SIZE=0x4000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=1
-default CONFIG_APIC_ID_OFFSET=0x10
-default CONFIG_LIFT_BSP_APIC_ID=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="ms9282"
-default CONFIG_MAINBOARD_VENDOR="MSI"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x9282
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_ID_SECTION_OFFSET=0x80
-
-### End Options.lb
-end