diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-10-23 12:07:58 +0200 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-11-20 17:38:23 +0000 |
| commit | e5b8a04f846874d3282923bf1bf15a2077bd440e (patch) | |
| tree | 094c257629ead4d1b298076aad6406a878fd16f3 /src/mainboard/msi | |
| parent | 1864f12fdaa62a042341180d7438e2b5daaa0904 (diff) | |
mainboard/msi/ms7d25: Configure NCT6687D pin for PECI
One register configuring multi-pin functions was outside of the Global
Configuration Registers space and skipped in the initial port patches.
Replicate the vendor configuration and set the Super I/O pin for PECI
functionality.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I90f142a1a9ee27dd061fc71b791bd4c7df97da6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68711
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/msi')
| -rw-r--r-- | src/mainboard/msi/ms7d25/bootblock.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/mainboard/msi/ms7d25/bootblock.c b/src/mainboard/msi/ms7d25/bootblock.c index 2dcb763827..110d6828a6 100644 --- a/src/mainboard/msi/ms7d25/bootblock.c +++ b/src/mainboard/msi/ms7d25/bootblock.c @@ -6,6 +6,7 @@ #include <superio/nuvoton/nct6687d/nct6687d.h> #define SERIAL_DEV PNP_DEV(0x4e, NCT6687D_SP1) +#define POWER_DEV PNP_DEV(0x4e, NCT6687D_SLEEP_PWR) void bootblock_mainboard_early_init(void) { @@ -13,6 +14,8 @@ void bootblock_mainboard_early_init(void) nuvoton_pnp_enter_conf_state(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low pnp_write_config(SERIAL_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low + + /* Below are multi-pin function */ pnp_write_config(SERIAL_DEV, 0x15, 0xaa); pnp_write_config(SERIAL_DEV, 0x1a, 0x02); pnp_write_config(SERIAL_DEV, 0x1b, 0x02); @@ -31,7 +34,12 @@ void bootblock_mainboard_early_init(void) pnp_write_config(SERIAL_DEV, 0x2b, 0x20); pnp_write_config(SERIAL_DEV, 0x2c, 0x8a); pnp_write_config(SERIAL_DEV, 0x2d, 0xaa); - nuvoton_pnp_exit_conf_state(SERIAL_DEV); + + pnp_set_logical_device(POWER_DEV); + /* Configure pin for PECI */ + pnp_write_config(POWER_DEV, 0xf3, 0x80); + + nuvoton_pnp_exit_conf_state(POWER_DEV); if (CONFIG(CONSOLE_SERIAL)) nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |