Use DIMM0 et al in lots more places instead of hardocding values.

The (0xa << 3) expression equals 0x50, i.e. DIMM0.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

4 files changed, 15 insertions, 12 deletions

diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
index 2aa7740998..ca31857382 100644
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -49,6 +49,7 @@
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "cpu/amd/dualcore/dualcore.c"
+#include <spd.h>
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
@@ -95,7 +96,7 @@ static void sio_setup(void)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
-		(0xa << 3) | 0, (0xa << 3) | 1, 0, 0,
+		DIMM0, DIMM1, 0, 0,
 		0, 0, 0, 0,
 		0, 0, 0, 0,
 		0, 0, 0, 0,
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index b37cd1f4bf..13dd4049b4 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -42,6 +42,7 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include <lib.h>
+#include <spd.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
@@ -117,11 +118,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
 		// Node 0
-		(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
-		(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
+		DIMM0, DIMM2, 0, 0,
+		DIMM1, DIMM3, 0, 0,
 		// Node 1
-		(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
-		(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
+		DIMM4, DIMM6, 0, 0,
+		DIMM5, DIMM7, 0, 0,
 	};
 
 	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index 74ec60af0a..5756b4c1c8 100644
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -109,9 +109,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
-                       //first node
-                        RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
-                        RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
+                      //first node
+                       RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
+                       RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
                        //second node
                        RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
                        RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index 6ec9daab18..e7754d0535 100644
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -45,6 +45,7 @@
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
+#include <spd.h>
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
@@ -132,11 +133,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
 		// Node 0
-		RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
-		RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
+		RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
+		RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
 		// node 1
-		RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
-		RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
+		RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
+		RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
 	};
 
 	unsigned bsp_apicid = 0;