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authorStefan Reinauer <stepan@coresystems.de>2010-04-14 11:40:34 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-14 11:40:34 +0000
commit5d3dee8334c2303434d7b00bec3aad4911120ac1 (patch)
tree38fd30e2473dc76d9cd64092133127934f184e9e /src/mainboard/msi
parent4154c668f24da79672099dfac06f5263c415fee0 (diff)
drop quite a lot of dead code that did nothing but produce warnings and make
the rest of the code unreadable. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/msi')
-rw-r--r--src/mainboard/msi/ms7135/irq_tables.c2
-rw-r--r--src/mainboard/msi/ms7135/romstage.c3
-rw-r--r--src/mainboard/msi/ms7260/romstage.c2
-rw-r--r--src/mainboard/msi/ms9185/romstage.c2
-rw-r--r--src/mainboard/msi/ms9282/romstage.c2
-rw-r--r--src/mainboard/msi/ms9652_fam10/romstage.c12
6 files changed, 5 insertions, 18 deletions
diff --git a/src/mainboard/msi/ms7135/irq_tables.c b/src/mainboard/msi/ms7135/irq_tables.c
index 2f213adab0..f43af44bf5 100644
--- a/src/mainboard/msi/ms7135/irq_tables.c
+++ b/src/mainboard/msi/ms7135/irq_tables.c
@@ -62,8 +62,6 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
pirq_info->rfu = rfu;
}
-void pci_assign_irqs(unsigned, unsigned, const unsigned char *);
-
/**
* Create the IRQ routing table.
* Values are derived from getpir generated code.
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
index 0a1c1d70bc..084f431948 100644
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -59,7 +59,7 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
@@ -98,7 +98,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void)
{
- unsigned value;
uint32_t dword;
uint8_t byte;
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 68e5ede3f7..25cde26dcb 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -75,7 +75,7 @@
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
/* Yes, on the MSI K9N Neo (MS-7260) the Super I/O is at 0x4e! */
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index 750cd27211..10135a5c50 100644
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -63,7 +63,7 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/nsc/pc87417/pc87417_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index 3949b67590..dad3624586 100644
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -58,7 +58,7 @@
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index fe00cebf7d..4a3e9f4c95 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -67,7 +67,7 @@
#include "northbridge/amd/amdfam10/debug.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
@@ -76,14 +76,6 @@
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
@@ -292,9 +284,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "enable_smbus()\n");
enable_smbus();
- post_code(0x3E);
- memreset_setup();
post_code(0x40);
printk(BIOS_DEBUG, "raminit_amdmct()\n");