newconfig is no more.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 0 insertions, 633 deletions

diff --git a/src/mainboard/msi/ms9282/Config.lb b/src/mainboard/msi/ms9282/Config.lb
deleted file mode 100644
index ec1211e7b4..0000000000
--- a/src/mainboard/msi/ms9282/Config.lb
+++ /dev/null
@@ -1,322 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## Copyright (C) 2006 MSI
-## Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_ROM_PAYLOAD = 1
-
-arch i386 end
-
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/ati/ragexl
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_USE_INIT
-
-makerule ./auto.o
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-end
-
-else
-
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-       action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-       action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/entry16.inc
-        ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-       if CONFIG_USE_INIT
-               ldscript /cpu/x86/32bit/entry32.lds
-       end
-
-       if CONFIG_USE_INIT
-               ldscript      /cpu/amd/car/cache_as_ram.lds
-       end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-       mainboardinit cpu/x86/16bit/reset16.inc
-       ldscript /cpu/x86/16bit/reset16.lds
-else
-       mainboardinit cpu/x86/32bit/reset32.inc
-       ldscript /cpu/x86/32bit/reset32.lds
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## ROMSTRAP table for MCP55
-##
-if CONFIG_USE_FALLBACK_IMAGE
-       mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-       ldscript /southbridge/nvidia/mcp55/romstrap.lds
-end
-
-##
-## Setup Cache-As-Ram
-##
-mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-       ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-
-# sample config for msi/ms9282
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_F
-                        device apic 0 on end
-                end
-        end
-
-       device pci_domain 0 on
-               chip northbridge/amd/amdk8 #mc0
-                       device pci 18.0 on #  northbridge
-                               #  devices on link 0, link 0 == LDT 0
-                               chip southbridge/nvidia/mcp55
-                                       device pci 0.0 on end   # HT
-                                       device pci 1.0 on # LPC
-                                               chip superio/winbond/w83627ehg
-                                                       device pnp 2e.0 on #  Floppy
-                                                               io 0x60 = 0x3f0
-                                                               irq 0x70 = 6
-                                                               drq 0x74 = 2
-                                                       end
-                                                       device pnp 2e.1 off #  Parallel Port
-                                                               io 0x60 = 0x378
-                                                               irq 0x70 = 7
-                                                       end
-                                                       device pnp 2e.2 on #  Com1
-                                                               io 0x60 = 0x3f8
-                                                               irq 0x70 = 4
-                                                       end
-                                                       device pnp 2e.3 off #  Com2
-                                                               io 0x60 = 0x2f8
-                                                               irq 0x70 = 3
-                                                       end
-                                                       device pnp 2e.5 on #  Keyboard
-                                                               io 0x60 = 0x60
-                                                               io 0x62 = 0x64
-                                                               irq 0x70 = 1
-                                                               irq 0x72 = 12
-                                                       end
-                                                       device pnp 2e.6 off #  SERIAL_FALSH
-                                                               io 0x60 = 0x100
-                                                       end
-                                                       device pnp 2e.7 off #  GAME_MIDI_GIPO1
-                                                               io 0x60 = 0x220
-                                                               io 0x62 = 0x300
-                                                               irq 0x70 = 9
-                                                       end
-                                                       device pnp 2e.8 off end #  WDTO_PLED
-                                                       device pnp 2e.9 off end #  GPIO2_GPIO3_GPIO4_GPIO5
-                                                       device pnp 2e.a off end #  ACPI
-                                                       device pnp 2e.b on #  HW Monitor
-                                                               io 0x60 = 0x290
-                                                               irq 0x70 = 5
-                                                       end
-                                               end
-                                       end
-                                        device pci 1.1 on # SM 0
-                                               chip drivers/i2c/i2cmux2 # pca9554 smbus mux
-                                                       device i2c 70 on  #0 pca9554 1
-                                                               chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 50 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 51 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 52 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 53 on end
-                                                                end
-                                                               chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 54 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 55 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 56 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 57 on end
-                                                                end
-                                                       end
-                                                       device i2c 70 on  #0 pca9554 2
-                                                               chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 50 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 51 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 52 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 53 on end
-                                                                end
-                                                               chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 54 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 55 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 56 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 57 on end
-                                                                end
-                                                       end
-                                               end
-                                       end
-                                       device pci 1.1 on # SM 1
-                                               chip drivers/i2c/i2cmux2 # pca9554 smbus mux
-                                                       device i2c 72 on     #pca9554 channle1
-                                                               chip drivers/i2c/adm1027   #HWM ADT7476 1
-                                                                       device i2c 2e on end
-                                                               end
-                                                       end
-                                                       device i2c 72 on     #pca9545 channel 2
-                                                               chip drivers/i2c/adm1027   #HWM ADT7463
-                                                                       device i2c 2e on end
-                                                               end
-                                                       end
-                                                       device i2c 72 on end  #pca9545 channel 3
-                                                       device i2c 72 on      #pca9545 channel 4
-                                                               chip drivers/i2c/adm1027   #HWM ADT7476 2
-                                                                       device i2c 2e on end
-                                                               end
-                                                       end
-                                               end
-                                       end
-
-                                       device pci 2.0 on end # USB 1.1
-                                       device pci 2.1 on end # USB 2
-                                       device pci 4.0 on  end # IDE
-                                               device pci 5.0 on  end # SATA 0
-                                       device pci 5.1 on  end # SATA 1
-                                       device pci 5.2 on  end # SATA 2
-                                       device pci 6.0 on  #P2P
-                                               device pci 4.0 on end
-                                       end # P2P
-                                       device pci 7.0 on end # reserve
-                                       device pci 8.0 on end # MAC0
-                                       device pci 9.0 on end # MAC1
-                                       device pci a.0 on
-                                               device pci 0.0 on
-                                                       device pci 4.0 on end  #pci_E lan1
-                                                       device pci 4.1 on end  #pci_E lan2
-                                               end
-                                       end # 0x376
-                                               device pci b.0 on  end # PCI E 0x374
-                                       device pci c.0 on  end
-                                       device pci d.0 on   #SAS
-                                               device pci 0.0 on end
-                                       end # PCI E 1 0x378
-                                       device pci e.0 on end # PCI E 0 0x375
-                                       device pci f.0 on end   #PCI E 0x377  pci_E slot
-                                       register "ide0_enable" = "1"
-                                       register "ide1_enable" = "1"
-                                       register "sata0_enable" = "1"
-                                       register "sata1_enable" = "1"
-                               end
-                       end #  device pci 18.0
-                       device pci 18.0 on end # Link 1
-                       device pci 18.0 on end
-                       device pci 18.1 on end
-                       device pci 18.2 on end
-                       device pci 18.3 on end
-               end #mc0
-
-       end # pci_domain
-
-#        chip drivers/generic/debug
-#                device pnp 0.0 off end
-#                device pnp 0.1 off end
-#                device pnp 0.2 off end
-#                device pnp 0.3 off end
-#                device pnp 0.4 off end
-#              device pnp 0.5 on end
-#        end
-end # root_complex
diff --git a/src/mainboard/msi/ms9282/Options.lb b/src/mainboard/msi/ms9282/Options.lb
deleted file mode 100644
index ee8be01679..0000000000
--- a/src/mainboard/msi/ms9282/Options.lb
+++ /dev/null
@@ -1,311 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 AMD
-## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
-##
-## Copyright (C) 2006 MSI
-## Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-#bx_b001- uses K8_HW_MEM_HOLE_SIZEK
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-#bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-#bx_b005+
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-
-# stepan 2007-04-12
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_ID_SECTION_OFFSET
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-#512K bytes
-default CONFIG_ROM_SIZE=524288
-
-#1M bytes
-#bx- default CONFIG_ROM_SIZE=1048576
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-#bx_b001- default K8_HW_MEM_HOLE_SIZEK=0x100000
-
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-
-##HT Unit ID offset, default is 1, the typical one
-default CONFIG_HT_CHAIN_UNITID_BASE=0x0
-
-##real SB Unit ID, default is 0x20, mean dont touch it at last
-#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0
-
-#make the SB HT chain on bus 0, default is not (0)
-#bx_b001- default K8_SB_HT_CHAIN_ON_BUS0=2
-
-##bx_b005+ make the SB HT chain on bus 0
-default CONFIG_SB_HT_CHAIN_ON_BUS0=1
-
-##only offset for SB chain?, default is yes(1)
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#VGA
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcc000
-default CONFIG_DCACHE_RAM_SIZE=0x4000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=1
-default CONFIG_APIC_ID_OFFSET=0x10
-default CONFIG_LIFT_BSP_APIC_ID=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="ms9282"
-default CONFIG_MAINBOARD_VENDOR="MSI"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x9282
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_ID_SECTION_OFFSET=0x80
-
-### End Options.lb
-end