Remove all AMD K8 boards

Platforms with LATE_CBMEM_INIT were agreed to be
removed with 4.7 release late 2017.

Change-Id: I0ecbb40f8c7ebdf68217f50af5624905d9005c64
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

11 files changed, 0 insertions, 1109 deletions

diff --git a/src/mainboard/msi/ms9185/Kconfig b/src/mainboard/msi/ms9185/Kconfig
deleted file mode 100644
index 355fdcfa35..0000000000
--- a/src/mainboard/msi/ms9185/Kconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-if BOARD_MSI_MS9185
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_AMD_SOCKET_F
-	select DIMM_DDR2
-	select DIMM_REGISTERED
-	select NORTHBRIDGE_AMD_AMDK8
-	select SOUTHBRIDGE_BROADCOM_BCM5780
-	select SOUTHBRIDGE_BROADCOM_BCM5785
-	select HT_CHAIN_DISTRIBUTE
-	select SUPERIO_NSC_PC87417
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
-	select LIFT_BSP_APIC_ID
-	select BOARD_ROMSIZE_KB_512
-	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
-	select QRANK_DIMM_SUPPORT
-	select SET_FIDVID
-
-config MAINBOARD_DIR
-	string
-	default msi/ms9185
-
-config DCACHE_RAM_BASE
-	hex
-	default 0xcc000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x04000
-
-config APIC_ID_OFFSET
-	hex
-	default 0x8
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "MS-9185"
-
-config MAX_CPUS
-	int
-	default 4
-
-config MAX_PHYSICAL_CPUS
-	int
-	default 2
-
-config HT_CHAIN_END_UNITID_BASE
-	hex
-	default 0x1
-
-config HT_CHAIN_UNITID_BASE
-	hex
-	default 0x6
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-endif # BOARD_MSI_MS9185
diff --git a/src/mainboard/msi/ms9185/Kconfig.name b/src/mainboard/msi/ms9185/Kconfig.name
deleted file mode 100644
index 00594c059d..0000000000
--- a/src/mainboard/msi/ms9185/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_MSI_MS9185
-	bool "MS-9185 (K9SD Master-S2R)"
diff --git a/src/mainboard/msi/ms9185/board_info.txt b/src/mainboard/msi/ms9185/board_info.txt
deleted file mode 100644
index e5081f9922..0000000000
--- a/src/mainboard/msi/ms9185/board_info.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Board name: K9SD Master-S2R (MS-9185)
-Category: server
-Board URL: http://www.msiserver.de/de/Produkte/Server_Mainboards/K9SD_Master_S2R_MS_9185.aspx
-Release year: 2006
diff --git a/src/mainboard/msi/ms9185/cmos.layout b/src/mainboard/msi/ms9185/cmos.layout
deleted file mode 100644
index e42037e1a1..0000000000
--- a/src/mainboard/msi/ms9185/cmos.layout
+++ /dev/null
@@ -1,52 +0,0 @@
-entries
-
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#392          3       r       0        unused
-395          1       e       1        hw_scrubber
-396          1       e       1        interleave_chip_selects
-397          2       e       8        max_mem_clock
-399         1       e       2        multi_core
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-440          4       e       9        slow_cpu
-444          1       e       1        nmi
-445          1       e       1        iommu
-456          1       e       1        ECC_memory
-728        256       h       0        user_data
-984         16       h       0        check_sum
-# Reserve the extended AMD configuration registers
-1000        24       r       0        amd_reserved
-
-
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-8     0     400Mhz
-8     1     333Mhz
-8     2     266Mhz
-8     3     200Mhz
-9     0     off
-9     1     87.5%
-9     2     75.0%
-9     3     62.5%
-9     4     50.0%
-9     5     37.5%
-9     6     25.0%
-9     7     12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/msi/ms9185/devicetree.cb b/src/mainboard/msi/ms9185/devicetree.cb
deleted file mode 100644
index 3c9168d2ee..0000000000
--- a/src/mainboard/msi/ms9185/devicetree.cb
+++ /dev/null
@@ -1,85 +0,0 @@
-chip northbridge/amd/amdk8/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/socket_F
-			device lapic 0 on end
-		end
-	end
-	device domain 0 on
-		subsystemid 0x1022 0x2b80 inherit
-		chip northbridge/amd/amdk8
-			device pci 18.0 on end
-			device pci 18.0 on end
-			device pci 18.0 on #  northbridge
-				#  devices on link 0
-				chip southbridge/broadcom/bcm5780 # HT2000
-					device pci 0.0 on end   # PXB 1 0x0130
-					device pci 1.0 on	# PXB 2 0x0130
-						device pci 4.0 on end # GB E 0x1668 vid = 0x14e4
-						device pci 4.1 on end # GB E 0x1669 vid = 0x14e4
-					end
-					device pci 2.0 on end # PCI E 1  #0x0132
-					device pci 3.0 on end # PCI E 2
-					device pci 4.0 on end # PCI E 3
-					device pci 5.0 on end # PCI E 4
-				end
-				chip southbridge/broadcom/bcm5785 # HT1000
-					device pci 0.0 on  # HT PXB  0x0036
-						device pci d.0 on end # PPBX 0x0104
-						device pci e.0 on end # SATA 0x024a
-						device pci e.1 on end # SATA 0x024a bx_a001
-						device pci e.2 on end # SATA 0x024a bx_a001
-						device pci e.3 on end # SATA 0x024a bx_a001
-					end
-					device pci 1.0 on # Legacy  pci main  0x0205
-					end
-					device pci 1.1 on end # IDE	 0x0214
-					device pci 1.2 on     # LPC	 0x0234
-						chip superio/nsc/pc87417
-							device  pnp 2e.0 off  # Floppy
-								io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 off  # Parallel Port
-								io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.2 off # Com 2
-								io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.3 on  # Com 1
-								io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.4 off end # SWC
-							device pnp 2e.5 off end # Mouse
-							device pnp 2e.6 on  # Keyboard
-								io 0x60 = 0x60
-								io 0x62 = 0x64
-								irq 0x70 = 1
-							end
-							device pnp 2e.7 off end # GPIO
-							device pnp 2e.f off end # XBUS
-							device pnp 2e.10 on #RTC
-								io 0x60 = 0x70
-								io 0x62 = 0x72
-							end
-						end
-					end
-					device pci 1.3 on end # WDTimer    0x0238
-					device pci 1.4 on end # XIOAPIC0   0x0235
-					device pci 1.5 on end # XIOAPIC1
-					device pci 1.6 on end # XIOAPIC2
-					device pci 2.0 on end # USB	 0x0223
-					device pci 2.1 on end # USB
-					device pci 2.2 on end # USB
-					device pci 3.0 on end # it is in bcm5785_0 bus
-				end
-			end #  device pci 18.0
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end # amdk8
-	end #domain
-end
diff --git a/src/mainboard/msi/ms9185/get_bus_conf.c b/src/mainboard/msi/ms9185/get_bus_conf.c
deleted file mode 100644
index d02f30687a..0000000000
--- a/src/mainboard/msi/ms9185/get_bus_conf.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
- *
- * Copyright (C) 2006 MSI
- * Written by bxshi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-#include <stdlib.h>
-#include "mb_sysconf.h"
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-struct mb_sysconf_t mb_sysconf;
-
-static unsigned pci1234x[] = {	//Here you only need to set value in pci1234 for HT-IO that could be installed or not
-	//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
-	0x0000ff0,
-	0x0000ff0,
-//        0x0000ff0,
-//        0x0000ff0,
-//        0x0000ff0,
-//        0x0000ff0,
-//        0x0000ff0,
-//        0x0000ff0
-};
-
-static unsigned hcdnx[] = {	//HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
-	0x20202020,
-	0x20202020,
-//        0x20202020,
-//        0x20202020,
-//        0x20202020,
-//        0x20202020,
-//        0x20202020,
-//        0x20202020,
-};
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
-
-	unsigned apicid_base;
-
-	struct device *dev;
-	int i;
-	struct mb_sysconf_t *m;
-
-	if (get_bus_conf_done == 1)
-		return;		//do it only once
-
-	get_bus_conf_done = 1;
-
-	sysconf.mb = &mb_sysconf;
-
-	m = sysconf.mb;
-
-	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
-
-	for (i = 0; i < sysconf.hc_possible_num; i++) {
-		sysconf.pci1234[i] = pci1234x[i];
-		sysconf.hcdn[i] = hcdnx[i];
-	}
-
-	get_sblk_pci1234();
-
-	sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
-	m->sbdn2 = sysconf.hcdn[0] & 0xff;	// bcm5780
-
-	m->bus_bcm5785_0 = (sysconf.pci1234[0] >> 16) & 0xff;
-	m->bus_bcm5780[0] = m->bus_bcm5785_0;
-
-	/* bcm5785 */
-	dev = dev_find_slot(m->bus_bcm5785_0, PCI_DEVFN(sysconf.sbdn, 0));
-	if (dev) {
-		m->bus_bcm5785_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-		dev = dev_find_slot(m->bus_bcm5785_1, PCI_DEVFN(0xd, 0));
-		if (dev) {
-			m->bus_bcm5785_1_1 =
-			    pci_read_config8(dev, PCI_SECONDARY_BUS);
-		}
-	} else {
-		printk(BIOS_DEBUG,
-		       "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
-		       m->bus_bcm5785_0, sysconf.sbdn);
-	}
-
-	/* bcm5780 */
-	for (i = 1; i < 7; i++) {
-		dev =
-		    dev_find_slot(m->bus_bcm5780[0],
-				  PCI_DEVFN(m->sbdn2 + i - 1, 0));
-		if (dev) {
-			m->bus_bcm5780[i] =
-			    pci_read_config8(dev, PCI_SECONDARY_BUS);
-		} else {
-			printk(BIOS_DEBUG,
-			       "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
-			       m->bus_bcm5780[0], m->sbdn2 + i - 1);
-		}
-	}
-
-/*I/O APICs:   APIC ID Version State           Address*/
-	if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
-		apicid_base = get_apicid_base(3);
-	else
-		apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
-	for (i = 0; i < 3; i++)
-		m->apicid_bcm5785[i] = apicid_base + i;
-}
diff --git a/src/mainboard/msi/ms9185/irq_tables.c b/src/mainboard/msi/ms9185/irq_tables.c
deleted file mode 100644
index 65f82a2823..0000000000
--- a/src/mainboard/msi/ms9185/irq_tables.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
- *
- * Copyright (C) 2006 MSI
- * Written by bxshi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-#include "mb_sysconf.h"
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
-			    uint8_t devfn, uint8_t link0, uint16_t bitmap0,
-			    uint8_t link1, uint16_t bitmap1, uint8_t link2,
-			    uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
-			    uint8_t slot, uint8_t rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	unsigned slot_num;
-	uint8_t *v;
-
-	uint8_t sum = 0;
-	int i;
-
-	struct mb_sysconf_t *m;
-
-	get_bus_conf();
-
-	m = sysconf.mb;
-
-	/* Align the table to be 16 byte aligned. */
-	addr += 15;
-	addr &= ~15;
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (uint8_t *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = m->bus_bcm5785_0;
-	pirq->rtr_devfn = (sysconf.sbdn << 3) | 0;
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1166;
-	pirq->rtr_device = 0x0036;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-//pci bridge
-	write_pirq_info(pirq_info, m->bus_bcm5785_0, (sysconf.sbdn << 3) | 0,
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
-	pirq_info++;
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "done.\n");
-
-	return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/msi/ms9185/mb_sysconf.h b/src/mainboard/msi/ms9185/mb_sysconf.h
deleted file mode 100644
index 6944c2465c..0000000000
--- a/src/mainboard/msi/ms9185/mb_sysconf.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
- * Copyright (C) 2006 MSI
- * Written by bxshi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef MB_SYSCONF_H
-#define MB_SYSCONF_H
-
-struct mb_sysconf_t {
-	unsigned char bus_bcm5780[7];
-	unsigned char bus_bcm5785_0;
-	unsigned char bus_bcm5785_1;
-	unsigned char bus_bcm5785_1_1;
-	unsigned apicid_bcm5785[3];
-
-	unsigned sbdn2;
-};
-
-#endif
diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c
deleted file mode 100644
index ea7c905af0..0000000000
--- a/src/mainboard/msi/ms9185/mptable.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2001 Eric W.Biederman <ebiderman@lnxi.com>
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
- *
- * Copyright (C) 2006 MSI
- * Written by bxshi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/io.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
-#include <cpu/amd/multicore.h>
-#endif
-#include <cpu/amd/amdk8_sysconf.h>
-#include "mb_sysconf.h"
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-
-	int i, bus_isa;
-	struct mb_sysconf_t *m;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	smp_write_processors(mc);
-
-	get_bus_conf();
-	m = sysconf.mb;
-
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs:   APIC ID Version State           Address*/
-	{
-		struct device *dev = NULL;
-		struct resource *res;
-		for (i = 0; i < 3; i++) {
-			dev = dev_find_device(0x1166, 0x0235, dev);
-			if (dev) {
-				res = find_resource(dev, PCI_BASE_ADDRESS_0);
-				if (res) {
-					smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11,
-							res2mmio(res, 0, 0));
-				}
-			}
-		}
-
-	}
-
-	mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0);
-
-//IDE
-	outb(0x02, 0xc00); outb(0x0e, 0xc01);
-
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-		m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe); // IDE
-
-//SATA
-	outb(0x07, 0xc00); outb(0x0f, 0xc01);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-		m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xf);
-
-//USB
-	outb(0x01, 0xc00); outb(0x0a, 0xc01);
-	for (i = 0; i < 3; i++)
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); //
-
-
-
-	/* enable int */
-	/* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
-	{
-		struct device *dev;
-		dev = dev_find_device(0x1166, 0x0205, 0);
-		if (dev) {
-			uint32_t dword;
-			dword = pci_read_config32(dev, 0x6c);
-			dword |= (1 << 4); // enable interrupts
-			pci_write_config32(dev, 0x6c, dword);
-		}
-		}
-
-//First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0
-	// AIC 8130 Galileo Technology...
-	for (i = 0; i < 4; i++)
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			m->bus_bcm5785_1_1, (6 << 2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); //
-
-
-//pci slot (on bcm5785)
-	for (i = 0; i < 4; i++)
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			m->bus_bcm5785_0, (5 << 2)|i, m->apicid_bcm5785[1], 8+i%4); //
-
-
-//onboard ati
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-		m->bus_bcm5785_0, (4 << 2)|0, m->apicid_bcm5785[1], 0x1);
-
-//PCI-X on bcm5780
-	for (i = 0; i < 4; i++)
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			m->bus_bcm5780[1], (4 << 2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); //
-
-//onboard Broadcom
-	for (i = 0; i < 2; i++)
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			m->bus_bcm5780[2], (4 << 2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); //
-
-
-// First PCI-E x8
-	for (i = 0; i < 4; i++)
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			m->bus_bcm5780[5], (0 << 2)|i, m->apicid_bcm5785[1], 0xe); //
-
-
-// Second PCI-E x8
-	for (i = 0; i < 4; i++)
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			m->bus_bcm5780[3], (0 << 2)|i, m->apicid_bcm5785[1], 0xc); //
-
-// Third PCI-E x1
-	for (i = 0; i < 4; i++)
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			m->bus_bcm5780[4], (0 << 2)|i, m->apicid_bcm5785[1], 0xd); //
-
-/*Local Ints:  Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
-	mptable_lintsrc(mc, bus_isa);
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/msi/ms9185/resourcemap.c b/src/mainboard/msi/ms9185/resourcemap.c
deleted file mode 100644
index 533f31a49a..0000000000
--- a/src/mainboard/msi/ms9185/resourcemap.c
+++ /dev/null
@@ -1,286 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2003 Stefan Reinauer <stepan@coresystems.de>
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
- *
- * Copyright (C) 2006 MSI
- * Written by bxshi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
- * ms9185  needs a different resource map
- *
- */
-
-static void setup_ms9185_resource_map(void)
-{
-	static const unsigned int register_values[] = {
-		/* Careful set limit registers before base registers which contain the enables */
-		/* DRAM Limit i Registers
-		 * F1:0x44 i = 0
-		 * F1:0x4C i = 1
-		 * F1:0x54 i = 2
-		 * F1:0x5C i = 3
-		 * F1:0x64 i = 4
-		 * F1:0x6C i = 5
-		 * F1:0x74 i = 6
-		 * F1:0x7C i = 7
-		 * [ 2: 0] Destination Node ID
-		 *         000 = Node 0
-		 *         001 = Node 1
-		 *         010 = Node 2
-		 *         011 = Node 3
-		 *         100 = Node 4
-		 *         101 = Node 5
-		 *         110 = Node 6
-		 *         111 = Node 7
-		 * [ 7: 3] Reserved
-		 * [10: 8] Interleave select
-		 *         specifies the values of A[14:12] to use with interleave enable.
-		 * [15:11] Reserved
-		 * [31:16] DRAM Limit Address i Bits 39-24
-		 *         This field defines the upper address bits of a 40 bit  address
-		 *         that define the end of the DRAM region.
-		 */
-		PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
-		PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
-		PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
-		PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
-		PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
-		PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
-		PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
-		/* DRAM Base i Registers
-		 * F1:0x40 i = 0
-		 * F1:0x48 i = 1
-		 * F1:0x50 i = 2
-		 * F1:0x58 i = 3
-		 * F1:0x60 i = 4
-		 * F1:0x68 i = 5
-		 * F1:0x70 i = 6
-		 * F1:0x78 i = 7
-		 * [ 0: 0] Read Enable
-		 *         0 = Reads Disabled
-		 *         1 = Reads Enabled
-		 * [ 1: 1] Write Enable
-		 *         0 = Writes Disabled
-		 *         1 = Writes Enabled
-		 * [ 7: 2] Reserved
-		 * [10: 8] Interleave Enable
-		 *         000 = No interleave
-		 *         001 = Interleave on A[12] (2 nodes)
-		 *         010 = reserved
-		 *         011 = Interleave on A[12] and A[14] (4 nodes)
-		 *         100 = reserved
-		 *         101 = reserved
-		 *         110 = reserved
-		 *         111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
-		 * [15:11] Reserved
-		 * [13:16] DRAM Base Address i Bits 39-24
-		 *         This field defines the upper address bits of a 40-bit address
-		 *         that define the start of the DRAM region.
-		 */
-		PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
-		/* Memory-Mapped I/O Limit i Registers
-		 * F1:0x84 i = 0
-		 * F1:0x8C i = 1
-		 * F1:0x94 i = 2
-		 * F1:0x9C i = 3
-		 * F1:0xA4 i = 4
-		 * F1:0xAC i = 5
-		 * F1:0xB4 i = 6
-		 * F1:0xBC i = 7
-		 * [ 2: 0] Destination Node ID
-		 *         000 = Node 0
-		 *         001 = Node 1
-		 *         010 = Node 2
-		 *         011 = Node 3
-		 *         100 = Node 4
-		 *         101 = Node 5
-		 *         110 = Node 6
-		 *         111 = Node 7
-		 * [ 3: 3] Reserved
-		 * [ 5: 4] Destination Link ID
-		 *         00 = Link 0
-		 *         01 = Link 1
-		 *         10 = Link 2
-		 *         11 = Reserved
-		 * [ 6: 6] Reserved
-		 * [ 7: 7] Non-Posted
-		 *         0 = CPU writes may be posted
-		 *         1 = CPU writes must be non-posted
-		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *         This field defines the upp adddress bits of a 40-bit address that
-		 *         defines the end of a memory-mapped I/O region n
-		 */
-		PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20,
-
-		/* Memory-Mapped I/O Base i Registers
-		 * F1:0x80 i = 0
-		 * F1:0x88 i = 1
-		 * F1:0x90 i = 2
-		 * F1:0x98 i = 3
-		 * F1:0xA0 i = 4
-		 * F1:0xA8 i = 5
-		 * F1:0xB0 i = 6
-		 * F1:0xB8 i = 7
-		 * [ 0: 0] Read Enable
-		 *         0 = Reads disabled
-		 *         1 = Reads Enabled
-		 * [ 1: 1] Write Enable
-		 *         0 = Writes disabled
-		 *         1 = Writes Enabled
-		 * [ 2: 2] Cpu Disable
-		 *         0 = Cpu can use this I/O range
-		 *         1 = Cpu requests do not use this I/O range
-		 * [ 3: 3] Lock
-		 *         0 = base/limit registers i are read/write
-		 *         1 = base/limit registers i are read-only
-		 * [ 7: 4] Reserved
-		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
-		 *         This field defines the upper address bits of a 40bit address
-		 *         that defines the start of memory-mapped I/O region i
-		 */
-		PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
-		/* PCI I/O Limit i Registers
-		 * F1:0xC4 i = 0
-		 * F1:0xCC i = 1
-		 * F1:0xD4 i = 2
-		 * F1:0xDC i = 3
-		 * [ 2: 0] Destination Node ID
-		 *         000 = Node 0
-		 *         001 = Node 1
-		 *         010 = Node 2
-		 *         011 = Node 3
-		 *         100 = Node 4
-		 *         101 = Node 5
-		 *         110 = Node 6
-		 *         111 = Node 7
-		 * [ 3: 3] Reserved
-		 * [ 5: 4] Destination Link ID
-		 *         00 = Link 0
-		 *         01 = Link 1
-		 *         10 = Link 2
-		 *         11 = reserved
-		 * [11: 6] Reserved
-		 * [24:12] PCI I/O Limit Address i
-		 *         This field defines the end of PCI I/O region n
-		 * [31:25] Reserved
-		 */
-		PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020,
-		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
-		/* PCI I/O Base i Registers
-		 * F1:0xC0 i = 0
-		 * F1:0xC8 i = 1
-		 * F1:0xD0 i = 2
-		 * F1:0xD8 i = 3
-		 * [ 0: 0] Read Enable
-		 *         0 = Reads Disabled
-		 *         1 = Reads Enabled
-		 * [ 1: 1] Write Enable
-		 *         0 = Writes Disabled
-		 *         1 = Writes Enabled
-		 * [ 3: 2] Reserved
-		 * [ 4: 4] VGA Enable
-		 *         0 = VGA matches Disabled
-		 *         1 = matches all address < 64K and where A[9:0] is in the
-		 *             range 3B0-3BB or 3C0-3DF independen of the base & limit registers
-		 * [ 5: 5] ISA Enable
-		 *         0 = ISA matches Disabled
-		 *         1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
-		 *             from matching agains this base/limit pair
-		 * [11: 6] Reserved
-		 * [24:12] PCI I/O Base i
-		 *         This field defines the start of PCI I/O region n
-		 * [31:25] Reserved
-		 */
-		PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
-		PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
-		/* Config Base and Limit i Registers
-		 * F1:0xE0 i = 0
-		 * F1:0xE4 i = 1
-		 * F1:0xE8 i = 2
-		 * F1:0xEC i = 3
-		 * [ 0: 0] Read Enable
-		 *         0 = Reads Disabled
-		 *         1 = Reads Enabled
-		 * [ 1: 1] Write Enable
-		 *         0 = Writes Disabled
-		 *         1 = Writes Enabled
-		 * [ 2: 2] Device Number Compare Enable
-		 *         0 = The ranges are based on bus number
-		 *         1 = The ranges are ranges of devices on bus 0
-		 * [ 3: 3] Reserved
-		 * [ 6: 4] Destination Node
-		 *         000 = Node 0
-		 *         001 = Node 1
-		 *         010 = Node 2
-		 *         011 = Node 3
-		 *         100 = Node 4
-		 *         101 = Node 5
-		 *         110 = Node 6
-		 *         111 = Node 7
-		 * [ 7: 7] Reserved
-		 * [ 9: 8] Destination Link
-		 *         00 = Link 0
-		 *         01 = Link 1
-		 *         10 = Link 2
-		 *         11 - Reserved
-		 * [15:10] Reserved
-		 * [23:16] Bus Number Base i
-		 *         This field defines the lowest bus number in configuration region i
-		 * [31:24] Bus Number Limit i
-		 *         This field defines the highest bus number in configuration regin i
-		 */
-		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000203,
-		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
-	};
-
-	int max;
-	max = ARRAY_SIZE(register_values);
-	setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
deleted file mode 100644
index d8cff07ff3..0000000000
--- a/src/mainboard/msi/ms9185/romstage.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Tyan
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
- *
- * Copyright (C) 2006 MSI
- * Written by bxshi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/broadcom/bcm5785/early_smbus.c"
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <reset.h>
-#include <cpu/x86/lapic.h>
-
-#include <superio/nsc/pc87417/pc87417.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
-#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
-
-unsigned get_sbdn(unsigned bus);
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-
-void activate_spd_rom(const struct mem_controller *ctrl)
-{
-#define SMBUS_SWITCH1 0x70
-#define SMBUS_SWITCH2 0x72
-	unsigned device = (ctrl->channel0[0]) >> 8;
-	smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
-	smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
-}
-
-int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "southbridge/broadcom/bcm5785/early_setup.c"
-#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <spd.h>
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-#define RC0 (0x10 << 8)
-#define RC1 (0x01 << 8)
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	static const uint16_t spd_addr[] = {
-		//first node
-		RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
-		RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
-		//second node
-		RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
-		RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
-	};
-
-	struct sys_info *sysinfo = &sysinfo_car;
-
-	int needs_reset;
-	unsigned bsp_apicid = 0;
-
-	if (!cpu_init_detectedx && boot_cpu()) {
-		/* Nothing special needs to be done to find bus 0 */
-		/* Allow the HT devices to be found */
-		enumerate_ht_chain();
-		bcm5785_enable_lpc();
-		//enable RTC
-		pc87417_enable_dev(RTC_DEV);
-	}
-
-	if (bist == 0)
-		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
-	pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
-
-	setup_ms9185_resource_map();
-
-	printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
-
-	setup_coherent_ht_domain();
-
-	wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
-	// It is said that we should start core1 after all core0 launched
-	/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
-	* So here need to make sure last core0 is started, esp for two way system,
-	* (there may be apic id conflicts in that case)
-	*/
-	start_other_cores();
-//bx_a010-     wait_all_other_cores_started(bsp_apicid);
-#endif
-
-	/* it will set up chains and store link pair for optimization later */
-	ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
-
-	bcm5785_early_setup();
-
-#if IS_ENABLED(CONFIG_SET_FIDVID)
-	{
-		msr_t msr;
-		msr = rdmsr(0xc0010042);
-		printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
-	}
-	enable_fid_change();
-	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-	init_fidvid_bsp(bsp_apicid);
-	// show final fid and vid
-	{
-		msr_t msr;
-		msr = rdmsr(0xc0010042);
-		printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
-	}
-#endif
-
-#if 1
-	needs_reset = optimize_link_coherent_ht();
-	needs_reset |= optimize_link_incoherent_ht(sysinfo);
-
-	// fidvid change will issue one LDTSTOP and the HT change will be effective too
-	if (needs_reset) {
-		printk(BIOS_INFO, "ht reset -\n");
-		soft_reset();
-	}
-#endif
-	allow_all_aps_stop(bsp_apicid);
-
-	//It's the time to set ctrl in sysinfo now;
-	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
-	enable_smbus();
-
-	//do we need apci timer, tsc...., only debug need it for better output
-	/* all ap stopped? */
-//        init_timer(); // Need to use TMICT to synchronize FID/VID
-
-	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
-}