diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2024-02-13 15:59:51 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-06 17:14:32 +0000 |
| commit | 84101434c0aae2562bab0231877f166a58ab2b95 (patch) | |
| tree | 4675c4ac95aa07aabff451374edd44047233948d /src/mainboard/msi/ms7e06/devicetree.cb | |
| parent | 0c6d48f3ee6f58c83f63053a8c0e60003f52ef2c (diff) | |
mb/msi/ms7d25,ms7e06: Enable discrete TPM module support
Now that multiple TPM drivers may be compiled in, it is possible to
support switching between fTPM and dTPM.
The patch adds:
- Device tree entry for PC80 discrete TPM
- TPM PIRQ# GPIO active low routed to IOAPIC for TPM interrupt
- MEMORY_MAPPED_TPM option to board's Kconfig to enable PC80 TPM driver
When the ME is disabled, e.g. via HECI command, chipset will route the
TPM traffic to SPI automatically. When a SPI TPM is connected to the
JTPM1 on the board, it will be probed successfully and initialized
in place of inactive PTT/fTPM.
Change-Id: Ie6e7026b6f1cec842bce4ef40b6db7feb75200e3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80456
Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/msi/ms7e06/devicetree.cb')
| -rw-r--r-- | src/mainboard/msi/ms7e06/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/msi/ms7e06/devicetree.cb b/src/mainboard/msi/ms7e06/devicetree.cb index 65ba314feb..cfe6b508f4 100644 --- a/src/mainboard/msi/ms7e06/devicetree.cb +++ b/src/mainboard/msi/ms7e06/devicetree.cb @@ -231,6 +231,9 @@ chip soc/intel/alderlake device pnp 4e.e off end # TACH/PWM assignment device pnp 4e.f off end # Function register end + chip drivers/pc80/tpm + device pnp 0.0 on end # TPM + end end device ref hda on subsystemid 0x1462 0x9e06 |