mainboard/ms7721: Copy files from "asus/f2a85-m" to "msi/ms7721".

This patch adds a copy of the Asus F2A85-M code with only minimal changes.
(to ensure that the code compiles)

A second commit will be published to remove the copied code parts that
don't apply to the MS-7221 and to make everything else actually work
on the MS-7221 board.

Change-Id: I1426c0876c7bfeb264231c0d338301133c721484
Signed-off-by: Renze Nicolai <renze@rnplus.nl>
Reviewed-on: https://review.coreboot.org/17494
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

1 files changed, 56 insertions, 0 deletions

diff --git a/src/mainboard/msi/ms7721/mainboard.c b/src/mainboard/msi/ms7721/mainboard.c
new file mode 100644
index 0000000000..2566037159
--- /dev/null
+++ b/src/mainboard/msi/ms7721/mainboard.c
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/amd/agesa/s3_resume.h>
+#include <cpu/x86/msr.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+
+/*************************************************
+ * enable the dedicated function in thatcher board.
+ *************************************************/
+static void mainboard_enable(device_t dev)
+{
+	msr_t msr;
+
+	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
+	msr = rdmsr(0xC0011020);
+	msr.lo &= ~(1 << 28);
+	wrmsr(0xC0011020, msr);
+
+	msr = rdmsr(0xC0011022);
+	msr.lo &= ~(1 << 4);
+	msr.lo &= ~(1 << 13);
+	wrmsr(0xC0011022, msr);
+
+	msr = rdmsr(0xC0011023);
+	msr.lo &= ~(1 << 23);
+	wrmsr(0xC0011023, msr);
+
+	if (acpi_is_wakeup_s3())
+		agesawrapper_fchs3earlyrestore();
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};