diff options
| author | Jonathan A. Kollasch <jakllsch@kollasch.net> | 2010-02-23 10:18:43 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-02-23 10:18:43 +0000 |
| commit | 040553f262bb34f6a51362e1f1fcad3fa91bfe9a (patch) | |
| tree | 3c06ee69c0a919cde77bca41583b8181ea80d268 /src/mainboard/msi/ms7135/devicetree.cb | |
| parent | 548dbe7bc88e60a4d1750de835532b84d7cdde96 (diff) | |
Adjust msi/ms7135 DCACHE_RAM_* config to previous 32KiB values,
4KiB is not enough to work.
Additionally, modify the device tree so that the undocumented LDN 6
is ignored by the resource allocator, and while here, assign the
parallel port DRQ, hardware monitor IRQ and drop NIC MAC address
on SMBus EEPROM hint, the ms7135 doesn't have such hardware.
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/msi/ms7135/devicetree.cb')
| -rw-r--r-- | src/mainboard/msi/ms7135/devicetree.cb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/msi/ms7135/devicetree.cb b/src/mainboard/msi/ms7135/devicetree.cb index d11bd9e2df..ac686db4d3 100644 --- a/src/mainboard/msi/ms7135/devicetree.cb +++ b/src/mainboard/msi/ms7135/devicetree.cb @@ -21,6 +21,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pnp 4e.1 on # Parallel port io 0x60 = 0x378 irq 0x70 = 7 + drq 0x74 = 3 end device pnp 4e.2 on # Com1 io 0x60 = 0x3f8 @@ -36,13 +37,14 @@ chip northbridge/amd/amdk8/root_complex # Root complex irq 0x70 = 1 irq 0x72 = 12 end + device pnp 4e.6 off end # XXX keep allocator happy device pnp 4e.7 off end # Game, MIDI, GPIO 1, GPIO 5 device pnp 4e.8 off end # GPIO 2 device pnp 4e.9 off end # GPIO 3, GPIO 4 device pnp 4e.a off end # ACPI device pnp 4e.b on # Hardware monitor io 0x60 = 0x290 - irq 0x70 = 0 + irq 0x70 = 5 end end end @@ -64,8 +66,6 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "ide1_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # register "mac_eeprom_smbus" = "3" - # register "mac_eeprom_addr" = "0x51" end end device pci 18.1 on end |