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authorCliff Huang <cliff.huang@intel.com>2024-08-20 11:27:34 -0700
committerFelix Held <felix-coreboot@felixheld.de>2024-09-06 13:36:57 +0000
commit216d8e19658881bce23014fc682185665c6e83e6 (patch)
treeb4d9b6025be2d91bb439f1587ba81c51d525af23 /src/mainboard/msi/Kconfig
parent516a31551ef3b4da9840ffa6354aef17bff12535 (diff)
soc/intel/common/gpio: vm index changes as PTL vm entries are not continuous
Add specific virtual wire mapping structure for: - First pad group does not starts with bit position 0. - vw_index and position are not continuous in between groups within a community. BUG= TEST=boot to OS and use iotools to read the registers that use 16-bit port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group ID field. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I986d4f4fe59b110e5075cab8742dfe8b336d034b Reviewed-on: https://review.coreboot.org/c/coreboot/+/83997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
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