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| author | Greg Watson <jarrah@users.sourceforge.net> | 2003-11-09 23:13:57 +0000 |
|---|---|---|
| committer | Greg Watson <jarrah@users.sourceforge.net> | 2003-11-09 23:13:57 +0000 |
| commit | 33ddaac6fda0b114f95b6fefc13e08639a7d0e19 (patch) | |
| tree | 8a81b8fc8fb3feb974dcdabf4b2d9fb10c342671 /src/mainboard/motorola | |
| parent | 91deab98a9adea9a4f2251ba73f46ca86f2acdaa (diff) | |
changes for v2
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1271 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/motorola')
| -rw-r--r-- | src/mainboard/motorola/sandpoint/Config.lb | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/src/mainboard/motorola/sandpoint/Config.lb b/src/mainboard/motorola/sandpoint/Config.lb index 19a884209e..74b8816052 100644 --- a/src/mainboard/motorola/sandpoint/Config.lb +++ b/src/mainboard/motorola/sandpoint/Config.lb @@ -7,7 +7,27 @@ uses CONFIG_SANDPOINT_TALUS uses CONFIG_SANDPOINT_UNITY uses CONFIG_SANDPOINT_VALIS uses CONFIG_SANDPOINT_GYRUS +uses PCIC0_CFGADDR +uses PCIC0_CFGDATA +uses PNP_CFGADDR +uses PNP_CFGDATA +## +## Set PCI registers +## +default PCIC0_CFGADDR=0xfec00000 +default PCIC0_CFGDATA=0xfee00000 +default PNP_CFGADDR=0x15c +default PNP_CFGDATA=0x15d + +## +## Early board initialization, called from ppc_main() +## +initobject init.c + +## +## Set our ARCH +## arch ppc end if CONFIG_SANDPOINT_ALTIMUS @@ -36,14 +56,12 @@ southbridge winbond/w83c553 end superio NSC/pc97307 register "com1" = "{1}" register "lpt" = "{0}" - register "port" = "SIO_COM1_BASE" + register "port" = "TTYS0_BASE" end ## ## Build the objects we have code for in this directory. ## -#object hardwaremain.o -object sandpoint.o dir nvram dir flash |