diff options
author | Michael Gold <mgold@ncf.ca> | 2009-07-05 19:29:39 +0000 |
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committer | Uwe Hermann <uwe@hermann-uwe.de> | 2009-07-05 19:29:39 +0000 |
commit | b70a45afd0eed934c3cd6a1f2abe162061173bfd (patch) | |
tree | 4c22d96d18c96d9805c54b188e2153dd610a5642 /src/mainboard/mitac/6513wu/Options.lb | |
parent | 3f1458ddd42911fa63d9f55c10cd57ed3953016b (diff) |
Add support for the Mitac 6513WU mainboard, a Compaq OEM board using the
i810 chipset. Not all hardware has been tested, but my test PC boots Linux
(via FILO) without any problems.
Also: Add support for the SMSC LPC47U33X to the generic 'smscsuperio' driver.
Signed-off-by: Michael Gold <mgold@ncf.ca>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/mitac/6513wu/Options.lb')
-rw-r--r-- | src/mainboard/mitac/6513wu/Options.lb | 110 |
1 files changed, 110 insertions, 0 deletions
diff --git a/src/mainboard/mitac/6513wu/Options.lb b/src/mainboard/mitac/6513wu/Options.lb new file mode 100644 index 0000000000..c065c5887f --- /dev/null +++ b/src/mainboard/mitac/6513wu/Options.lb @@ -0,0 +1,110 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Michael Gold <mgold@ncf.ca> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses CC +uses CONFIG_CBFS +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_CONSOLE_SERIAL8250 +uses CONFIG_CONSOLE_VGA +uses CONFIG_CROSS_COMPILE +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_FALLBACK_SIZE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HEAP_SIZE +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_OBJCOPY +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_PCI_ROM_RUN +uses CONFIG_RAMBASE +uses CONFIG_ROMBASE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_PAYLOAD +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_ROM_SECTION_OFFSET +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_INIT +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_XIP_ROM_SIZE +uses COREBOOT_EXTRA_VERSION +uses HOSTCC + +# Motherboard info, tables, etc. +default CONFIG_MAINBOARD_VENDOR = "Mitac" +default CONFIG_MAINBOARD_PART_NUMBER = "6513WU" +default CONFIG_IRQ_SLOT_COUNT = 8 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_OPTION_TABLE = 0 +default CONFIG_USE_OPTION_TABLE = 0 + +# ROM layout +default CONFIG_ROM_SIZE = 512 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_ROM_PAYLOAD = 1 +default CONFIG_CBFS = 0 + +# RAM layout +default CONFIG_RAMBASE = 0x00004000 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 + +# Misc. settings +default CONFIG_USE_INIT = 0 +default CONFIG_HAVE_HARD_RESET = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 + +# Compiler setup +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" + +# Console settings +default CONFIG_CONSOLE_SERIAL8250 = 1 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 7 # No debugging/spew +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 + +# Enable onboard video +default CONFIG_CONSOLE_VGA = 1 +default CONFIG_PCI_ROM_RUN = 1 + +end |