diff options
| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-06-10 00:15:31 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-06-12 18:40:59 +0000 |
| commit | a2977ae72d7711fa24592f9e64d3ed62c3028664 (patch) | |
| tree | 56fb15c90fd1beca45ee3c0623f9f941e229746a /src/mainboard/lippert | |
| parent | 7368da32e73db28ccb92945f8bbef2bfe11b2a6c (diff) | |
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for v3197
Update FSP headers for Tiger Lake platform generated based FSP
version 3197 to include below additional UPD:
FSP-M:
SkipCpuReplacementCheck
PCH HSIO Tuning UPDs
FSP-S:
PcieRpHotPlug
TccActivationOffset
TccOffsetClamp
TccOffsetLock
TccOffsetTimeWindowForRatl
USB3 HSIO Tuning UPDs
BUG=none
BRANCH=none
TEST=build and boot volteer
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ib40d226dd2ecc4fb34965e1f2c416c53edef01d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42243
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/lippert')
0 files changed, 0 insertions, 0 deletions