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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-09-20 13:41:49 -0600
committerFelix Held <felix-coreboot@felixheld.de>2022-02-10 12:52:41 +0000
commitc585d8c96cf8cecec2239087c803323616242163 (patch)
tree37301bde34e42fcca09d641421539597cd0e37d3 /src/mainboard/lippert
parent9048043302e7c694240806792fa929f6e0820419 (diff)
soc/intel/common: Add Crash Log and PMC SRAM PCI device IDs
Add Alder Lake and Tiger Lake specific Crash Log and PMC SRAM device IDs. Document Number: 619501, 645548 Change-Id: I64b58b8c345bd54774c4dab7b65258714cd8dc9e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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