diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-04-22 16:46:31 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-04-28 18:36:35 +0200 |
| commit | 2458f42b27e6525f4131899ef36f21d0f7dace1a (patch) | |
| tree | b3f5ece33c604ddc9638da1f192b3e8361216d65 /src/mainboard/lippert | |
| parent | cf7b4989083cb3fd1adf34dc5e07d4ac253e8f85 (diff) | |
AMD: Add common header file for CAR setup
Change-Id: I24b2cbd671ac3a463562d284f06258140a019a37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4683
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/lippert')
| -rw-r--r-- | src/mainboard/lippert/frontrunner-af/romstage.c | 3 | ||||
| -rw-r--r-- | src/mainboard/lippert/toucan-af/romstage.c | 3 |
2 files changed, 2 insertions, 4 deletions
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 9ecd0872bc..16fb8ab21b 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -29,6 +29,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/early_serial.c" @@ -42,8 +43,6 @@ #include "cpu/amd/mtrr.h" #include "cpu/amd/agesa/s3_resume.h" -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 4f62268e0e..9f8cf1ade3 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -29,6 +29,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/winbond/w83627dhg/w83627dhg.h" @@ -42,8 +43,6 @@ #include "cpu/amd/mtrr.h" #include "cpu/amd/agesa/s3_resume.h" -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1) |