LiPPERT Toucan-AF [2/2]: actually implement mainboard support

Step 2: change the Persimmon code to adapt it to the new board's hardware.

The Toucan-AF is a COM Express Compact Type 6 form factor embedded board:
- AMD Fusion G-T56N (1.65 GHz dual core) or T40R (1 GHz single core) APU
  - 1-4 GB DDR3 memory down
  - 1x VGA, 2x DisplayPort (1 switchable to LVDS)
- AMD A55E (Hudson-E1) southbridge
  - 8x USB 2.0
  - 4x SATA
  - HD Audio (with codec on baseboard)
  - NEC uPD78F0532 microcontroller on I2C ("SEMA")
- 7x PCIe2.0 x1 (1 on PEG)
- Intel I210 GbE (on APU PCIe x1, can be disabled for additional PCIe)
- 2x SST 25VF032B (SO8, soldered) 4 MB SPI flash (BIOS and failsafe BIOS)

The Toucan-AF has no SIO on board.  This patch includes basic support for a
Winbond W83627DHG (PS/2, 2x RS232), because the ADLINK ExpressBase-6 used
for evaluation happens to have one.  The code may have to be adapted to the
actual baseboard of the application.

http://www.adlinktech.com/PD/web/PD_detail.php?pid=1132

Change-Id: I9041b905bad45852ac9b402fcbd5decbc98b377b
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2572
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 3 insertions, 3 deletions

diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 2ed4a77d25..7d1181383a 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -31,7 +31,7 @@
 #include <console/loglevel.h>
 #include "agesawrapper.h"
 #include "cpu/x86/bist.h"
-#include "superio/fintek/f81865f/f81865f_early_serial.c"
+#include "superio/winbond/w83627dhg/w83627dhg.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "drivers/pc80/i8254.c"
 #include "drivers/pc80/i8259.c"
@@ -45,7 +45,7 @@
 void disable_cache_as_ram(void); /* cache_as_ram.inc */
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
-#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
+#define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -70,7 +70,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		sb_Poweron_Init();
 
 		post_code(0x31);
-		f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+		w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 		console_init();
 	}