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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-06-04 06:49:00 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2018-06-05 12:44:12 +0000
commit64aa881263fa3fdec827a3f7adf04b138ab82ff1 (patch)
treef23ae6c0868089cc443d12cec2618f471c0efe77 /src/mainboard/lippert/spacerunner-lx
parent88af0f38eb19f956e8df2b62254c10c7603a9a33 (diff)
amd/geode_lx: Remove most boards
There is active work to convert remaining two boards, PC Engines alix1c and alix2d, to EARLY_CBMEM_INIT. Change-Id: I87e3963af7ef719e9fa2a8b0df34a896265905f0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/lippert/spacerunner-lx')
-rw-r--r--src/mainboard/lippert/spacerunner-lx/Kconfig49
-rw-r--r--src/mainboard/lippert/spacerunner-lx/Kconfig.name2
-rw-r--r--src/mainboard/lippert/spacerunner-lx/board_info.txt6
-rw-r--r--src/mainboard/lippert/spacerunner-lx/devicetree.cb90
-rw-r--r--src/mainboard/lippert/spacerunner-lx/irq_tables.c71
-rw-r--r--src/mainboard/lippert/spacerunner-lx/mainboard.c82
-rw-r--r--src/mainboard/lippert/spacerunner-lx/romstage.c181
7 files changed, 0 insertions, 481 deletions
diff --git a/src/mainboard/lippert/spacerunner-lx/Kconfig b/src/mainboard/lippert/spacerunner-lx/Kconfig
deleted file mode 100644
index 65645fdbf0..0000000000
--- a/src/mainboard/lippert/spacerunner-lx/Kconfig
+++ /dev/null
@@ -1,49 +0,0 @@
-if BOARD_LIPPERT_SPACERUNNER_LX
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_GEODE_LX
- select NORTHBRIDGE_AMD_LX
- select SOUTHBRIDGE_AMD_CS5536
- select SUPERIO_ITE_IT8712F
- select HAVE_DEBUG_SMBUS
- select HAVE_PIRQ_TABLE
- select PIRQ_ROUTE
- select UDELAY_TSC
- # Board is equipped with a 1 MB SPI flash, however, due to limitations
- # of the IT8712F Super I/O, only the top 512 KB are directly mapped.
- select BOARD_ROMSIZE_KB_512
- select POWER_BUTTON_FORCE_ENABLE
- select PLL_MANUAL_CONFIG
- select CORE_GLIU_500_400
-
-config MAINBOARD_DIR
- string
- default lippert/spacerunner-lx
-
-config MAINBOARD_PART_NUMBER
- string
- default "Cool SpaceRunner-LX"
-
-config IRQ_SLOT_COUNT
- int
- default 7
-
-config ONBOARD_UARTS_RS485
- bool "Switch on-board serial ports to RS485"
- default n
- help
- If selected, both on-board serial ports will operate in RS485 mode
- instead of RS232.
-
-config ONBOARD_IDE_SLAVE
- bool "Make on-board SSD act as Slave"
- default n
- help
- If selected, the on-board SSD will act as IDE Slave instead of Master.
-
-config PLLMSRlo
- hex
- default 0x00de6001
-
-endif # BOARD_LIPPERT_SPACERUNNER_LX
diff --git a/src/mainboard/lippert/spacerunner-lx/Kconfig.name b/src/mainboard/lippert/spacerunner-lx/Kconfig.name
deleted file mode 100644
index 85eec96382..0000000000
--- a/src/mainboard/lippert/spacerunner-lx/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_LIPPERT_SPACERUNNER_LX
- bool "Cool SpaceRunner-LX"
diff --git a/src/mainboard/lippert/spacerunner-lx/board_info.txt b/src/mainboard/lippert/spacerunner-lx/board_info.txt
deleted file mode 100644
index 76be510bb6..0000000000
--- a/src/mainboard/lippert/spacerunner-lx/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Category: half
-Board URL: http://www.adlinktech.com/PD/web/PD_detail.php?pid=1148
-ROM package: SOIC8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: n
diff --git a/src/mainboard/lippert/spacerunner-lx/devicetree.cb b/src/mainboard/lippert/spacerunner-lx/devicetree.cb
deleted file mode 100644
index 5f5b15bbb6..0000000000
--- a/src/mainboard/lippert/spacerunner-lx/devicetree.cb
+++ /dev/null
@@ -1,90 +0,0 @@
-chip northbridge/amd/lx
- device domain 0 on
- device pci 1.0 on end # Northbridge
- device pci 1.1 on end # Graphics
- device pci 1.2 on end # AES
- chip southbridge/amd/cs5536
- # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK
- # SIRQ Mode = Active(Quiet) mode. Save power....
- # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse,
- # UARTs, etc IRQs. OK
- register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010
- register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above
- register "lpc_serirq_mode" = "1"
- register "enable_gpio_int_route" = "0x0D0C0700"
- register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
- register "enable_USBP4_device" = "0" # 0:host, 1:device
- register "enable_USBP4_overcurrent" = "0" # 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
- register "com1_enable" = "0"
- register "com1_address" = "0x3E8"
- register "com1_irq" = "6"
- register "com2_enable" = "0"
- register "com2_address" = "0x2E8"
- register "com2_irq" = "6"
- register "unwanted_vpci[0]" = "0x80007B00" # Audio: 1 << 31 + Device 0x0F << 11 + Function 3 << 8
- register "unwanted_vpci[1]" = "0" # End of list has a zero
- device pci 8.0 on end # Slot4
- device pci 9.0 on end # Slot3
- device pci a.0 on end # Slot2
- device pci b.0 on end # Slot1
- device pci c.0 on end # IT8888
- device pci e.0 on end # Ethernet
- device pci f.0 on # ISA Bridge
- chip superio/ite/it8712f
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.2 on # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.3 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.4 on # EC
- io 0x60 = 0x290 # EC
- io 0x62 = 0x298 # PME
- irq 0x70 = 9
- end
- device pnp 2e.5 on # PS/2 keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 2e.6 on # PS/2 mouse
- irq 0x70 = 12
- end
- device pnp 2e.7 on # GPIO
- io 0x62 = 0x1220 # Simple I/O
- io 0x64 = 0x1228 # SPI
- end
- device pnp 2e.8 off # MIDI
- io 0x60 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.9 off # Game port
- io 0x60 = 0x220
- end
- device pnp 2e.a off end # CIR
- end
- end
- device pci f.2 on end # IDE
- device pci f.3 off end # Audio
- device pci f.4 on end # OHCI
- device pci f.5 on end # EHCI
- end
- end
- # APIC cluster is late CPU init.
- device cpu_cluster 0 on
- chip cpu/amd/geode_lx
- device lapic 0 on end
- end
- end
-end
diff --git a/src/mainboard/lippert/spacerunner-lx/irq_tables.c b/src/mainboard/lippert/spacerunner-lx/irq_tables.c
deleted file mode 100644
index 37e82e5cf4..0000000000
--- a/src/mainboard/lippert/spacerunner-lx/irq_tables.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 LiPPERT Embedded Computers GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Based on irq_tables.c from AMD's DB800 mainboard. */
-
-#include <arch/pirq_routing.h>
-#include <console/console.h>
-#include <arch/io.h>
-#include <arch/pirq_routing.h>
-#include "southbridge/amd/cs5536/cs5536.h"
-
-/* Platform IRQs */
-#define PIRQA 10
-#define PIRQB 11
-#define PIRQC 5
-#define PIRQD 15
-
-/* Map */
-#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
-#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
-#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
-#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
-
-/* Link */
-#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
-#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
-#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
-#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
- 0x00, /* IRQs devoted exclusively to PCI usage */
- 0x100B, /* Vendor */
- 0x002B, /* Device */
- 0, /* Miniport data */
- {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
- 0xE0, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
- {
- /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
- {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
- {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
- {0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, /* slot1 */
- {0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x2, 0x0}, /* slot2 */
- {0x00, (0x09 << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x3, 0x0}, /* slot3 */
- {0x00, (0x08 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x4, 0x0}, /* slot4 */
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/lippert/spacerunner-lx/mainboard.c b/src/mainboard/lippert/spacerunner-lx/mainboard.c
deleted file mode 100644
index 594545d146..0000000000
--- a/src/mainboard/lippert/spacerunner-lx/mainboard.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 LiPPERT Embedded Computers GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Based on mainboard.c from AMD's DB800 mainboard. */
-
-#include <stdlib.h>
-#include <stdint.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <arch/io.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-/* Bit0 turns off the Live LED, bit1 switches Com1 to RS485, bit2 same for Com2. */
-#if IS_ENABLED(CONFIG_ONBOARD_UARTS_RS485)
- #define SIO_GP1X_CONFIG 0x07
-#else
- #define SIO_GP1X_CONFIG 0x01
-#endif
-
-static const u16 ec_init_table[] = { /* hi = data, lo = index */
- 0x1900, /* Enable monitoring */
- 0x3050, /* VIN4,5 enabled */
- 0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */
- 0x805C, /* Unlock zero adjust */
- 0x7056, 0x3C57, /* Zero adjust TMPIN1,2 */
- 0x005C, /* Lock zero adjust */
- 0xD014 /* Also set FAN_CTL polarity to Active High */
-};
-
-static void init(struct device *dev)
-{
- unsigned int gpio_base, i;
- printk(BIOS_DEBUG, "LiPPERT SpaceRunner-LX ENTER %s\n", __func__);
-
- /* Init CS5536 GPIOs */
- gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;
-
- outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD#
- outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD#
- outl(0x04000000, gpio_base + 0x18); // GPIO10 pull up 0 - THRM_ALRM#
- outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM#
- outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM#
- outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz
- outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz
- outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - 32kHz
-
- /* Init Environment Controller. */
- for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) {
- u16 val = ec_init_table[i];
- outb((u8)val, 0x0295);
- outb(val >> 8, 0x0296);
- }
-
- /* bit2 = RS485_EN2, bit1 = RS485_EN1, bit0 = Live LED */
- outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */
-
- printk(BIOS_DEBUG, "LiPPERT SpaceRunner-LX EXIT %s\n", __func__);
-}
-
-static void mainboard_enable(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c
deleted file mode 100644
index a8885700ef..0000000000
--- a/src/mainboard/lippert/spacerunner-lx/romstage.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- * Copyright (C) 2008 LiPPERT Embedded Computers GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Based on romstage.c from AMD's DB800 and DBM690T mainboards. */
-
-#include <stdlib.h>
-#include <stdint.h>
-#include <spd.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <console/console.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/lxdef.h>
-#include <southbridge/amd/cs5536/cs5536.h>
-#include <southbridge/amd/cs5536/smbus.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8712f/it8712f.h>
-#include <northbridge/amd/lx/raminit.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
-
-/* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */
-#if IS_ENABLED(CONFIG_ONBOARD_IDE_SLAVE)
- #define SMC_CONFIG 0x03
-#else
- #define SMC_CONFIG 0x01
-#endif
-
-static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I
- 0xFF, 0xFF, // only values used by Geode-LX raminit.c are set
- [SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, // (Fundamental) memory type
- [SPD_NUM_ROWS] = 0x0D, // Number of row address bits [13]
- [SPD_NUM_COLUMNS] = 0x0A, // Number of column address bits [10]
- [SPD_NUM_DIMM_BANKS] = 1, // Number of module rows (banks)
- 0xFF, 0xFF, 0xFF,
- [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 0x50, // SDRAM cycle time (highest CAS latency), RAS access time (tRAC) [5.0 ns in BCD]
- 0xFF, 0xFF,
- [SPD_REFRESH] = 0x82, // Refresh rate/type [Self Refresh, 7.8 us]
- [SPD_PRIMARY_SDRAM_WIDTH] = 64, // SDRAM width (primary SDRAM) [64 bits]
- 0xFF, 0xFF, 0xFF,
- [SPD_NUM_BANKS_PER_SDRAM] = 4, // SDRAM device attributes, number of banks on SDRAM device
- [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x1C, // SDRAM device attributes, CAS latency [3, 2.5, 2]
- 0xFF, 0xFF,
- [SPD_MODULE_ATTRIBUTES] = 0x20, // SDRAM module attributes [differential clk]
- [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0x40, // SDRAM device attributes, general [Concurrent AP]
- [SPD_SDRAM_CYCLE_TIME_2ND] = 0x60, // SDRAM cycle time (2nd highest CAS latency) [6.0 ns in BCD]
- 0xFF,
- [SPD_SDRAM_CYCLE_TIME_3RD] = 0x75, // SDRAM cycle time (3rd highest CAS latency) [7.5 ns in BCD]
- 0xFF,
- [SPD_tRP] = 60, // Min. row precharge time [15 ns in units of 0.25 ns]
- [SPD_tRRD] = 40, // Min. row active to row active [10 ns in units of 0.25 ns]
- [SPD_tRCD] = 60, // Min. RAS to CAS delay [15 ns in units of 0.25 ns]
- [SPD_tRAS] = 40, // Min. RAS pulse width = active to precharge delay [40 ns]
- [SPD_BANK_DENSITY] = 0x40, // Density of each row on module [256 MB]
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- [SPD_tRFC] = 70 // SDRAM Device Minimum Auto Refresh to Active/Auto Refresh [70 ns]
-};
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
- if (device != DIMM0)
- return 0xFF; /* No DIMM1, don't even try. */
-
-#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
- if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
- printk(BIOS_ERR, "ERROR: spd_read_byte(DIMM0, 0x%02x) "
- "returns 0xff\n", address);
- }
-#endif
-
- /* Fake SPD ROM value */
- return (address < sizeof(spdbytes)) ? spdbytes[address] : 0xFF;
-}
-
-/* Send config data to System Management Controller via SMB. */
-static int smc_send_config(unsigned char config_data)
-{
- if (smbus_check_stop_condition(SMBUS_IO_BASE))
- return 1;
- if (smbus_start_condition(SMBUS_IO_BASE))
- return 2;
- if (smbus_send_slave_address(SMBUS_IO_BASE, 0x50)) // SMC address
- return 3;
- if (smbus_send_command(SMBUS_IO_BASE, 0x28)) // set config data
- return 4;
- if (smbus_send_command(SMBUS_IO_BASE, 0x01)) // data length
- return 5;
- if (smbus_send_command(SMBUS_IO_BASE, config_data))
- return 6;
- smbus_stop_condition(SMBUS_IO_BASE);
- return 0;
-}
-
-#include "northbridge/amd/lx/pll_reset.c"
-#include "cpu/amd/geode_lx/cpureginit.c"
-#include "cpu/amd/geode_lx/syspreinit.c"
-#include "cpu/amd/geode_lx/msrinit.c"
-
-static const u16 sio_init_table[] = { // hi = data, lo = index
- 0x072C, // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal
- 0x1423, // don't delay PoWeROK1/2
- 0x9072, // watchdog triggers PWROK, counts seconds
-#if !IS_ENABLED(CONFIG_USE_WATCHDOG_ON_BOOT)
- 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0
-#endif
- 0xBF25, 0x172A, 0xF326, // select GPIO function for most pins
- 0xFF27, 0xDF28, 0x2729, // (GP45 = SUSB, GP23,22,16,15 = SPI, GP13 = PWROK1)
- 0x66B8, 0x0CB9, // enable pullups on SPI, RS485_EN
- 0x07C0, // enable Simple-I/O for GP12-10= RS485_EN2,1, LIVE_LED
- 0x07C8, // config GP12-10 as output
- 0x2DF5, // map Hw Monitor Thermal Output to GP55
- 0x08F8, // map GP LED Blinking 1 to GP10 = LIVE_LED (deactivate Simple I/O to use)
-};
-
-/* Early mainboard specific GPIO setup. */
-static void mb_gpio_init(void)
-{
- int i;
-
- /* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */
- for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
- u16 reg = sio_init_table[i];
- ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8));
- }
-}
-
-void asmlinkage mainboard_romstage_entry(unsigned long bist)
-{
- int err;
-
- static const struct mem_controller memctrl[] = {
- {.channel0 = {DIMM0, DIMM1}}
- };
-
- SystemPreInit();
- msr_init();
-
- cs5536_early_setup();
-
- /*
- * Note: Must do this AFTER the early_setup! It is counting on some
- * early MSR setup for CS5536.
- */
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- mb_gpio_init();
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- pll_reset();
-
- cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
-
- /* bit1 = on-board IDE is slave, bit0 = Spread Spectrum */
- if ((err = smc_send_config(SMC_CONFIG))) {
- printk(BIOS_ERR, "ERROR %d sending config data to SMC\n", err);
- }
-
- sdram_initialize(1, memctrl);
-
- /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
- return;
-}