mb/lippert: Put files under variants/

This isn't reproducible for some reason, but it is relatively simple.

Change-Id: I507229be71ac2c589c7ecd81495d38ce363d26a7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43275
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

10 files changed, 785 insertions, 0 deletions

diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/BiosCallOuts.c
new file mode 100644
index 0000000000..b2a96a236f
--- /dev/null
+++ b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/BiosCallOuts.c
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <AGESA.h>
+#include <console/console.h>
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <SB800.h>
+#include <southbridge/amd/cimx/sb800/gpio_oem.h>
+
+/* Should AGESA_GNB_PCIE_SLOT_RESET use agesa_NoopSuccess?
+ *
+ * Dedicated reset is not needed for the on-board Intel I210 GbE controller.
+ */
+
+static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+	{AGESA_DO_RESET,			agesa_Reset },
+	{AGESA_READ_SPD,			agesa_ReadSpd },
+	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
+	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
+	{AGESA_GNB_PCIE_SLOT_RESET,		agesa_NoopUnsupported },
+	{AGESA_HOOKBEFORE_DRAM_INIT,		board_BeforeDramInit },
+	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,	agesa_NoopSuccess },
+	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
+	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
+};
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
+
+/*	Call the host environment interface to provide a user hook opportunity. */
+static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+{
+	MEM_DATA_STRUCT *MemData = ConfigPtr;
+
+	printk(BIOS_INFO, "Setting DDR3 voltage: ");
+	FCH_IOMUX(184) = 2; // GPIO184: VMEM_LV_EN# lowers VMEM from 1.5 to 1.35V
+	switch (MemData->ParameterListPtr->DDR3Voltage) {
+	case VOLT1_25: // board is not able to provide this
+		MemData->ParameterListPtr->DDR3Voltage = VOLT1_35; // sorry
+		printk(BIOS_INFO, "can't provide 1.25 V, using ");
+		// fall through
+	default: // AGESA.h says in mixed case 1.5V DIMMs get excluded
+	case VOLT1_35:
+		FCH_GPIO(184) = 0x08; // = output, disable PU, set to 0
+		printk(BIOS_INFO, "1.35 V\n");
+		break;
+	case VOLT1_5:
+		FCH_GPIO(184) = 0xC8; // = output, disable PU, set to 1
+		printk(BIOS_INFO, "1.5 V\n");
+	}
+
+	return AGESA_SUCCESS;
+}
diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/OemCustomize.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/OemCustomize.c
new file mode 100644
index 0000000000..c1b571e713
--- /dev/null
+++ b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/OemCustomize.c
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <AGESA.h>
+#include <PlatformMemoryConfiguration.h>
+
+#include <northbridge/amd/agesa/state_machine.h>
+
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
+		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 5,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
+		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 6,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
+		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
+	}
+};
+
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+	// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeTravisDpToLvds, Aux1, Hdp1)
+	},
+	// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
+	}
+};
+
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList,
+};
+
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+	InitEarly->GnbConfig.PsppPolicy		= 0;
+}
+
+/*----------------------------------------------------------------------------------------
+ *						CUSTOMER OVERRIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ *	Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ *	(e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ *	is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ *	use its default conservative settings.
+ */
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
+	HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B),
+	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
+	NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
+	PSO_END
+};
+
+void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
+{
+	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c
new file mode 100644
index 0000000000..070da4e7b5
--- /dev/null
+++ b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <northbridge/amd/agesa/state_machine.h>
+#include <superio/smsc/smscsuperio/smscsuperio.h>
+
+#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
+
+void bootblock_mainboard_early_init(void)
+{
+	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/devicetree.cb b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/devicetree.cb
new file mode 100644
index 0000000000..a1d15c398f
--- /dev/null
+++ b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/devicetree.cb
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/amd/agesa/family14/root_complex
+	device cpu_cluster 0 on
+		chip cpu/amd/agesa/family14
+			device lapic 0 on end
+		end
+	end
+	device domain 0 on
+		subsystemid 0x1022 0x1510 inherit
+		chip northbridge/amd/agesa/family14
+			device pci 0.0 on end # Root Complex
+			device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
+			device pci 4.0 on end # PCIE P2P bridge on-board NIC
+			device pci 5.0 off end # PCIE P2P bridge
+			device pci 6.0 off end # PCIE P2P bridge
+			device pci 7.0 off end # PCIE P2P bridge
+			device pci 8.0 off end # NB/SB Link P2P bridge
+		end # agesa northbridge
+
+		chip southbridge/amd/cimx/sb800
+			device pci 11.0 on end # SATA
+			device pci 12.0 on end # OHCI USB 0-4
+			device pci 12.2 on end # EHCI USB 0-4
+			device pci 13.0 on end # OHCI USB 5-9
+			device pci 13.2 on end # EHCI USB 5-9
+			device pci 14.0 on end # SM
+			device pci 14.1 off end # IDE	0x439c
+			device pci 14.2 on end # HDA	0x4383
+			device pci 14.3 on # LPC		0x439d
+				chip superio/smsc/smscsuperio
+					device pnp 4e.0 off end		# Floppy
+					device pnp 4e.3 off end		# Parallel Port
+					device pnp 4e.4 on		# COM1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 4e.5 on		# COM2
+						io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 4e.7 on		# Keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+						irq 0x72 = 12
+					end
+					device pnp 4e.A on		# Runtime Regs
+						io 0x60 = 0x0E00
+						drq 0xF0 = 0x0B # no 32kHz
+					end
+				end # smscsuperio
+			end #LPC
+
+			device pci 14.4 on  end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
+			device pci 14.5 off end # OHCI FS/LS USB
+			device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
+			device pci 15.0 off end # PCIe PortA
+			device pci 15.1 off end # PCIe PortB
+			device pci 15.2 off end # PCIe PortC
+			device pci 15.3 off end # PCIe PortD
+			device pci 16.0 on  end # OHCI USB 10-13
+			device pci 16.2 on  end # EHCI USB 10-13
+
+			register "gpp_configuration" = "4" #1:1:1:1
+			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+		end	#southbridge/amd/cimx/sb800
+
+		chip northbridge/amd/agesa/family14
+
+			# These seem unnecessary
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+			device pci 18.5 on end
+			device pci 18.6 on end
+			device pci 18.7 on end
+
+			register "spdAddrLookup" = "
+			{
+				{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+			}"
+		end # agesa northbridge
+
+	end #domain
+end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c
new file mode 100644
index 0000000000..71d0f415df
--- /dev/null
+++ b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdlib.h>
+#include <amdblocks/acpimmio.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <device/mmio.h>
+#include <device/pci_ops.h>
+#include <device/pci_def.h>
+#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
+#include <vendorcode/amd/cimx/sb800/OEM.h> /* SMBUS0_BASE_ADDRESS */
+#include <southbridge/amd/cimx/sb800/gpio_oem.h>
+#include "sema.h"
+
+/* Init SIO GPIOs. */
+#define SIO_RUNTIME_BASE 0x0E00
+static const u16 sio_init_table[] = { // hi = offset, lo = value
+	0x4BA0, // GP1x: COM1/2 control   = RS232, no term, max 115200
+	0x2300, // GP10: COM1 termination = push/pull output
+	0x2400, // GP11: COM2 termination = push/pull output
+	0x2500, // GP12: COM1 RS485 mode  = push/pull output
+	0x2600, // GP13: COM2 RS485 mode  = push/pull output
+	0x2700, // GP14: COM1 speed A     = push/pull output
+	0x2900, // GP15: COM1 speed B     = push/pull output
+	0x2A00, // GP16: COM2 speed A     = push/pull output
+	0x2B00, // GP17: COM2 speed B     = push/pull output
+
+	0x3904, // GP36                   = KBDRST# function
+
+	0x4E74, // GP4x: Ethernet enable  = on
+	0x6E84, // GP44: Ethernet enable  = open drain output
+
+	// GP5x = COM2 function instead of GPIO
+	0x3F05, 0x4005, 0x4105, 0x4204, 0x4305, 0x4404, 0x4505, 0x4604,
+
+	0x470C, // GP60                   = WDT function
+	0x5E00, // LED2: Live LED         = off
+	0x4884, // GP61: Live LED         = LED2 function
+
+	0x5038, // GP6x: USB power        = 3x on
+	0x5580, // GP63: USB power 0/1    = open drain output
+	0x5680, // GP64: USB power 2/3    = open drain output
+	0x5780, // GP65: USB power 4/5    = open drain output
+};
+
+static void init(struct device *dev)
+{
+	volatile u8 *spi_base;	/* base addr of Hudson's SPI host controller */
+	int i;
+	printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " ENTER %s\n", __func__);
+
+	/* Init Hudson GPIOs. */
+	printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE);
+	/* GPIO50: FCH_ARST#_GATE resets stuck PCIe devices */
+	iomux_write8(50, 2);
+	/* output set to 1 as it's never needed */
+	iomux_write8(50, 0xc0);
+	/* GPIO197: BIOS_DEFAULTS# = input (int. PU) */
+	iomux_write8(197, 2);
+	/* GPIO58-56: REV_ID2-0 */
+	iomux_write8(56, 1);
+	/* inputs, disable int. pull-ups */
+	gpio_100_write8(56, 0x28);
+	iomux_write8(57, 1);
+	gpio_100_write8(57, 0x28);
+	iomux_write8(58, 1);
+	gpio_100_write8(58, 0x28);
+	/* "Gpio96": GEVENT0# signal on X2 connector (int. PU) */
+	iomux_write8(96, 1);
+	/* GPIO52,61,62,187-192 free to use on X2 connector */
+	iomux_write8(52, 1);
+	/* default to inputs with int. PU */
+	iomux_write8(61, 2);
+	iomux_write8(62, 2);
+	iomux_write8(187, 2);
+	iomux_write8(188, 2);
+	iomux_write8(189, 1);
+	iomux_write8(190, 1);
+	iomux_write8(191, 1);
+	iomux_write8(192, 1);
+	/* just in case anyone cares */
+	if (!fch_gpio_state(197))
+		printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n");
+	printk(BIOS_INFO, "Board revision ID: %u\n",
+	       fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56));
+
+	/* Init SIO GPIOs. */
+	printk(BIOS_DEBUG, "Init SIO GPIOs @ 0x%04x\n", SIO_RUNTIME_BASE);
+	for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
+		u16 val = sio_init_table[i];
+		outb((u8)val, SIO_RUNTIME_BASE + (val >> 8));
+	}
+
+	/* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */
+	spi_base = (u8 *)((uintptr_t)pci_read_config32(pcidev_on_root(0x14, 3),
+							   0xA0) & 0xFFFFFFE0);
+	/* NormSpeed in SPI_Cntrl1 register */
+	spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20;
+
+	/*
+	 * Notify the SMC we're alive and kicking, or after a while it will
+	 * effect a power cycle and switch to the alternate BIOS chip.
+	 * Should be done as late as possible.
+	 * Failure here does not matter if watchdog was already disabled,
+	 * by configuration or previous boot, so ignore return value.
+	 */
+	sema_send_alive();
+
+	printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " EXIT %s\n", __func__);
+}
+
+/**********************************************
+ * Enable the dedicated functions of the board.
+ **********************************************/
+static void mainboard_enable(struct device *dev)
+{
+	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+	dev->ops->init = init;
+
+	/* enable GPP CLK0 */
+	/* disable GPP CLK1 thru SLT_GFX_CLK */
+	misc_write8(0, 0x0f);
+	misc_write8(1, 0);
+	misc_write8(2, 0);
+	misc_write8(3, 0);
+	misc_write8(4, 0);
+
+	/*
+	 * Initialize ASF registers to an arbitrary address because someone
+	 * long ago set things up this way inside the SPD read code.  The
+	 * SPD read code has been made generic and moved out of the board
+	 * directory, so the ASF init is being done here.
+	 */
+	pm_write8(0x29, 0x80);
+	pm_write8(0x28, 0x61);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/BiosCallOuts.c
new file mode 100644
index 0000000000..4861809ba6
--- /dev/null
+++ b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/BiosCallOuts.c
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <AGESA.h>
+#include <console/console.h>
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <SB800.h>
+#include <southbridge/amd/cimx/sb800/gpio_oem.h>
+
+/* Should AGESA_GNB_PCIE_SLOT_RESET use agesa_NoopSuccess?
+ *
+ * COM Express doesn't provide dedicated resets for individual lanes
+ * and it's not needed for the on-board Intel I210 GbE controller.
+ */
+
+static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+	{AGESA_DO_RESET,			agesa_Reset },
+	{AGESA_READ_SPD,			agesa_ReadSpd },
+	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
+	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
+	{AGESA_GNB_PCIE_SLOT_RESET,		agesa_NoopUnsupported },
+	{AGESA_HOOKBEFORE_DRAM_INIT,		board_BeforeDramInit },
+	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,	agesa_NoopSuccess },
+	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
+	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
+};
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
+
+/*	Call the host environment interface to provide a user hook opportunity. */
+static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+{
+	MEM_DATA_STRUCT *MemData = ConfigPtr;
+
+	printk(BIOS_INFO, "Setting DDR3 voltage: ");
+	FCH_IOMUX(65) = 1; // GPIO65: VMEM_LV_EN# lowers VMEM from 1.5 to 1.35V
+	switch (MemData->ParameterListPtr->DDR3Voltage) {
+	case VOLT1_25: // board is not able to provide this
+		MemData->ParameterListPtr->DDR3Voltage = VOLT1_35; // sorry
+		printk(BIOS_INFO, "can't provide 1.25 V, using ");
+		// fall through
+	default: // AGESA.h says in mixed case 1.5V DIMMs get excluded
+	case VOLT1_35:
+		FCH_GPIO(65) = 0x08; // = output, disable PU, set to 0
+		printk(BIOS_INFO, "1.35 V\n");
+		break;
+	case VOLT1_5:
+		FCH_GPIO(65) = 0xC8; // = output, disable PU, set to 1
+		printk(BIOS_INFO, "1.5 V\n");
+	}
+
+	return AGESA_SUCCESS;
+}
diff --git a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/OemCustomize.c b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/OemCustomize.c
new file mode 100644
index 0000000000..e3ffe9b39b
--- /dev/null
+++ b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/OemCustomize.c
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <AGESA.h>
+#include <PlatformMemoryConfiguration.h>
+
+#include <northbridge/amd/agesa/state_machine.h>
+
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
+	}
+};
+
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+	// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeAutoDetect, Aux1, Hdp1)
+	},
+	// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeAutoDetect, Aux2, Hdp2)
+	}
+};
+
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList,
+};
+
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+	InitEarly->GnbConfig.PsppPolicy		= 0;
+}
+
+/*----------------------------------------------------------------------------------------
+ *						CUSTOMER OVERRIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ *	Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ *	(e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ *	is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ *	use its default conservative settings.
+ */
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
+	HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B),
+	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
+	NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
+	PSO_END
+};
+
+void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
+{
+	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
diff --git a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/bootblock.c b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/bootblock.c
new file mode 100644
index 0000000000..5077db799b
--- /dev/null
+++ b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/bootblock.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627dhg/w83627dhg.h>
+
+#define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1)
+
+void bootblock_mainboard_early_init(void)
+{
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/devicetree.cb b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/devicetree.cb
new file mode 100644
index 0000000000..ee8b246ef1
--- /dev/null
+++ b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/devicetree.cb
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/amd/agesa/family14/root_complex
+	device cpu_cluster 0 on
+		chip cpu/amd/agesa/family14
+			device lapic 0 on end
+		end
+	end
+	device domain 0 on
+		subsystemid 0x1022 0x1510 inherit
+		chip northbridge/amd/agesa/family14
+			device pci 0.0 on end # Root Complex
+			device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
+			device pci 4.0 on end # PCIE P2P bridge
+			device pci 5.0 on end # PCIE P2P bridge
+			device pci 6.0 on end # PCIE P2P bridge
+			device pci 7.0 on end # PCIE P2P bridge on-board NIC
+			device pci 8.0 off end # NB/SB Link P2P bridge
+		end # agesa northbridge
+
+		chip southbridge/amd/cimx/sb800
+			device pci 11.0 on end # SATA
+			device pci 12.0 on end # OHCI USB 0-4
+			device pci 12.2 on end # EHCI USB 0-4
+			device pci 13.0 on end # OHCI USB 5-9
+			device pci 13.2 on end # EHCI USB 5-9
+			device pci 14.0 on end # SM
+			device pci 14.1 off end # IDE	0x439c
+			device pci 14.2 on end # HDA	0x4383
+			device pci 14.3 on # LPC		0x439d
+				chip superio/winbond/w83627dhg
+					device pnp 4e.0 off end		# Floppy
+					device pnp 4e.1 off end		# Parallel Port
+					device pnp 4e.2 on		# COM1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 4e.3 on		# COM2
+						io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 4e.5 on		# Keyboard, Mouse
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+						irq 0x72 = 12
+					end
+					#device pnp 4e.6 off end	# SPI
+					device pnp 4e.307 off end	# GPIO6
+					device pnp 4e.8 off end		# WDTO, PLED
+					device pnp 4e.009 off end	# GPIO2
+					device pnp 4e.109 off end	# GPIO3
+					device pnp 4e.209 off end	# GPIO4
+					device pnp 4e.309 off end	# GPIO5
+					device pnp 4e.A off end		# ACPI
+					device pnp 4e.B off end		# HW Monitor
+				end # w83627dhg
+			end #LPC
+			device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
+			device pci 14.5 off end # OHCI FS/LS USB
+			device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
+			device pci 15.0 on  end # PCIe PortA
+			device pci 15.1 on  end # PCIe PortB
+			device pci 15.2 on  end # PCIe PortC
+			device pci 15.3 on  end # PCIe PortD
+			device pci 16.0 off end # OHCI USB 10-13
+			device pci 16.2 off end # EHCI USB 10-13
+			register "gpp_configuration" = "4" #1:1:1:1
+			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+		end	#southbridge/amd/cimx/sb800
+
+		chip northbridge/amd/agesa/family14
+
+			# These seem unnecessary
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+			device pci 18.5 on end
+			device pci 18.6 on end
+			device pci 18.7 on end
+
+			register "spdAddrLookup" = "
+			{
+				{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+			}"
+		end # agesa northbridge
+
+	end #domain
+end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c
new file mode 100644
index 0000000000..901ee0208f
--- /dev/null
+++ b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/acpimmio.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/mmio.h>
+#include <device/pci_ops.h>
+#include <device/pci_def.h>
+#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
+#include <vendorcode/amd/cimx/sb800/OEM.h> /* SMBUS0_BASE_ADDRESS */
+#include <southbridge/amd/cimx/sb800/gpio_oem.h>
+#include "mainboard/lippert/frontrunner-af/sema.h"
+
+static void init(struct device *dev)
+{
+	volatile u8 *spi_base;	/* base addr of Hudson's SPI host controller */
+	printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " ENTER %s\n", __func__);
+
+	/* Init Hudson GPIOs. */
+	printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE);
+	/* GPIO50: FCH_ARST#_GATE resets stuck PCIe devices */
+	iomux_write8(50, 2);
+	/* output set to 1 as it's never needed */
+	iomux_write8(50, 0xc0);
+	/* GPIO197: BIOS_DEFAULTS# = input (int. PU) */
+	iomux_write8(197, 2);
+	/* input, disable int. pull-up */
+	gpio_100_write8(197, 0x28);
+	/* GPIO58-56: REV_ID2-0 */
+	iomux_write8(56, 1);
+	/* inputs, disable int. pull-ups */
+	gpio_100_write8(56, 0x28);
+	iomux_write8(57, 1);
+	gpio_100_write8(57, 0x28);
+	iomux_write8(58, 1);
+	gpio_100_write8(58, 0x28);
+	/* GPIO187,188,166,GPO160: GPO0-3 on COM Express connector */
+	iomux_write8(187, 2);
+	/* outputs, disable PUs, default to 0 */
+	gpio_100_write8(187, 0x08);
+	iomux_write8(188, 2);
+	gpio_100_write8(188, 0x08);
+	iomux_write8(166, 2);
+	gpio_100_write8(166, 0x08);
+	/*
+	 * needed to make GPO160 work (Hudson Register Reference
+	 * section 2.3.6.1)
+	 */
+	pm_write8(0xdc, pm_read8(0xdc) & (~0x80));
+	pm_write8(0xe6, (pm_read8(0xe6) & (~0x02)) | 1);
+	iomux_write8(160, 1);
+	gpio_100_write8(160, 0x08);
+	/* GPIO189-192: GPI0-3 on COM Express connector */
+	iomux_write8(189, 1);
+	/* default to inputs with int. PU */
+	iomux_write8(190, 1);
+	iomux_write8(191, 1);
+	iomux_write8(192, 1);
+
+	/* just in case anyone cares */
+	if (!fch_gpio_state(197))
+		printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n");
+	printk(BIOS_INFO, "Board revision ID: %u\n",
+	       fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56));
+
+	/* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */
+	spi_base = (u8 *)((uintptr_t)pci_read_config32(pcidev_on_root(0x14, 3),
+							   0xA0) & 0xFFFFFFE0);
+	/* NormSpeed in SPI_Cntrl1 register */
+	spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20;
+
+	/*
+	 * Notify the SMC we're alive and kicking, or after a while it will
+	 * effect a power cycle and switch to the alternate BIOS chip.
+	 * Should be done as late as possible.
+	 * Failure here does not matter if watchdog was already disabled,
+	 * by configuration or previous boot, so ignore return value.
+	 */
+	sema_send_alive();
+
+	printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " EXIT %s\n", __func__);
+}
+
+/**********************************************
+ * Enable the dedicated functions of the board.
+ **********************************************/
+static void mainboard_enable(struct device *dev)
+{
+	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+	dev->ops->init = init;
+
+	/* enable GPP CLK0 thru CLK1 */
+	/* disable GPP CLK2 thru SLT_GFX_CLK */
+	misc_write8(0, 0xff);
+	misc_write8(1, 0);
+	misc_write8(2, 0);
+	misc_write8(3, 0);
+	misc_write8(4, 0);
+
+	/*
+	 * Initialize ASF registers to an arbitrary address because someone
+	 * long ago set things up this way inside the SPD read code.  The
+	 * SPD read code has been made generic and moved out of the board
+	 * directory, so the ASF init is being done here.
+	 */
+	pm_write8(0x29, 0x80);
+	pm_write8(0x28, 0x61);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};