diff options
| author | Jens Rottmann <JRottmann@LiPPERTembedded.de> | 2013-02-28 10:24:20 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-02 00:16:04 +0100 |
| commit | 23d13b1d454a6482d436cc65f50bb367c027c10f (patch) | |
| tree | f04969de66f9aee28844254007733d1f4e35bc5d /src/mainboard/lippert/frontrunner-af/romstage.c | |
| parent | 73d4965be99cc93cec277afca4cdae979433b2b0 (diff) | |
LiPPERT FrontRunner-AF [2/2]: actually implement mainboard support
Step 2: change the Persimmon code to adapt it to the new board's hardware.
The FrontRunner-AF is a PC/104+ form factor embedded board:
- AMD Fusion G-T56N (1.65 GHz dual core) or T40R (1 GHz single core) APU
- DDR3 SO-DIMM socket (1.5 or 1.35V)
- VGA and LVDS (via Analogix ANX3110)
- AMD A55E (Hudson-E1) southbridge
- 6x USB 2.0
- 1x SATA, 1x CFast socket
- HD Audio (via Realtek ALC886)
- PCI and ISA (via ITE IT8888)
- NEC uPD78F0532 microcontroller on I2C ("SEMA")
- Intel I210 GbE (on APU PCIe x1)
- SMSC SCH3112 SIO
- PS/2
- 2x RS232/485
- 2x SST 25VF032B (SO8, soldered) 4 MB SPI flash (BIOS and failsafe BIOS)
http://www.adlinktech.com/PD/web/PD_detail.php?pid=1131
Change-Id: Id55f89d224ad669b351c36128b12299802b721ba
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2553
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/lippert/frontrunner-af/romstage.c')
| -rw-r--r-- | src/mainboard/lippert/frontrunner-af/romstage.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 2ed4a77d25..e5b3aeb311 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -31,7 +31,7 @@ #include <console/loglevel.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/fintek/f81865f/f81865f_early_serial.c" +#include "superio/smsc/smscsuperio/early_serial.c" #include "cpu/x86/lapic/boot_cpu.c" #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" @@ -45,7 +45,7 @@ void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) +#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -70,7 +70,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } |