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authorRonald G. Minnich <rminnich@gmail.com>2016-10-25 19:11:07 -0700
committerRonald G. Minnich <rminnich@gmail.com>2016-10-28 21:09:06 +0200
commit66bea528cfde9dea3d84ca571b7cca94964850c4 (patch)
tree85ec37cf2e6b423fbdf1511c84dad389aa96ea08 /src/mainboard/linutop
parentaa75cdc1b2e887f0dbc47b4e1cdbcad6a4972f8b (diff)
riscv: add the lowrisc/nexys4ddr mainboard
This was tested at the coreboot meeting in Berlin. The uart programming may still not be right but when used with the lowrisc bitstream for the board we were able to load and start linux, although it does not yet get far due to PTE version issues with lowrisc. Change-Id: Ia1de1a92762631c9d7bb3d41b04f95296144caa3 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17132 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
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