diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-06-23 00:25:18 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-06-26 11:43:56 +0000 |
| commit | 6c83a71b0a803c922b02b613e927d4c49b944c32 (patch) | |
| tree | 176f163e7fdeaaf1032c853e87ce5571bd921be7 /src/mainboard/libretrend/lt1000 | |
| parent | c7c8cf2edd713fd578423bc043403ae4f91e2e29 (diff) | |
skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Diffstat (limited to 'src/mainboard/libretrend/lt1000')
| -rw-r--r-- | src/mainboard/libretrend/lt1000/devicetree.cb | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index dd2fc6084c..d6bc99078b 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -125,24 +125,6 @@ chip soc/intel/skylake register "PcieRpClkSrcNumber[10]" = "3" register "PcieRpClkSrcNumber[11]" = "3" - register "usb2_ports" = "{ - [0] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */ - [1] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */ - [2] = USB2_PORT_MID(OC_SKIP), /* WiFi */ - [3] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */ - [4] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */ - [5] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */ - [6] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */ - [7] = USB2_PORT_MID(OC_SKIP), /* GL850G for F_USB1 and F_USB2 headers */ - }" - - register "usb3_ports" = "{ - [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */ - [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */ - [2] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */ - [3] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */ - }" - # PL2 override 25W register "power_limits_config" = "{ .tdp_pl2_override = 25, @@ -154,7 +136,25 @@ chip soc/intel/skylake device domain 0 on device ref igpu on end device ref sa_thermal on end - device ref south_xhci on end + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */ + [1] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */ + [2] = USB2_PORT_MID(OC_SKIP), /* WiFi */ + [3] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */ + [4] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */ + [5] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */ + [6] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */ + [7] = USB2_PORT_MID(OC_SKIP), /* GL850G for F_USB1 and F_USB2 headers */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */ + [3] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */ + }" + end device ref south_xdci on end device ref thermal on end device ref heci1 on end |