diff options
| author | Felix Singer <felixsinger@posteo.net> | 2023-10-23 17:37:21 +0200 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2023-10-28 18:42:46 +0000 |
| commit | 9a1b47e8a005e87ed6be0c8d62c62e5e7007b3e3 (patch) | |
| tree | 6ecd08976f478d5e7f3984637bf59e984ac00998 /src/mainboard/libretrend/lt1000/devicetree.cb | |
| parent | d5008a2e8289ff98a42f27a0f263e0fd0b47bfc2 (diff) | |
mb/{sm/x11,razor,libretrend}/dt: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.
Don't convert the settings for PCIe root ports as they will be moved
into the devicetree to their related root ports at some later point.
While on it, remove superfluous comments related to modified lines.
Change-Id: I27bac17098beb8b6cb3942e68a37da0095f0d0bd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/mainboard/libretrend/lt1000/devicetree.cb')
| -rw-r--r-- | src/mainboard/libretrend/lt1000/devicetree.cb | 45 |
1 files changed, 26 insertions, 19 deletions
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 26feab441c..09da24cc2a 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -34,12 +34,16 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[1]" = "0" - register "SataPortsDevSlp[2]" = "0" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + }" + register "SataPortsDevSlp" = "{ + [0] = 0, + [1] = 0, + [2] = 0, + }" register "SataSpeedLimit" = "2" register "DspEnable" = "1" register "IoBufferOwnership" = "0" @@ -129,20 +133,23 @@ chip soc/intel/skylake register "PcieRpClkSrcNumber[10]" = "3" register "PcieRpClkSrcNumber[11]" = "3" + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */ + [1] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */ + [2] = USB2_PORT_MID(OC_SKIP), /* WiFi */ + [3] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */ + [4] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */ + [5] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */ + [6] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */ + [7] = USB2_PORT_MID(OC_SKIP), /* GL850G for F_USB1 and F_USB2 headers */ + }" - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # WiFi - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # F_USB3 header - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # F_USB3 header - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left) - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left) - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # GL850G for F_USB1 and F_USB2 headers - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right) - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right) - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */ + [3] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */ + }" # PL2 override 25W register "power_limits_config" = "{ |