diff options
author | Felix Singer <felixsinger@posteo.net> | 2024-06-23 20:32:15 +0200 |
---|---|---|
committer | Felix Singer <felixsinger@posteo.net> | 2024-06-26 11:44:13 +0000 |
commit | 4b7220398923af42fa39a7fcb532daf797510f77 (patch) | |
tree | f338082fc94ba81015f56348d48fe159fc238201 /src/mainboard/libretrend/lt1000/devicetree.cb | |
parent | df7de392ef5f8e1654df96a1a050820eb3779012 (diff) |
skl mainboards/dt: Move serirq setting into LPC device scope
Change-Id: I84da5365907664ce223dec4adb22a8f1a6e2a144
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83188
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard/libretrend/lt1000/devicetree.cb')
-rw-r--r-- | src/mainboard/libretrend/lt1000/devicetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 02c35386c8..2ebc67024e 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -9,8 +9,6 @@ chip soc/intel/skylake register "eist_enable" = "1" - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Set the Thermal Control Circuit (TCC) activation value to 95C # even though FSP integration guide says to set it to 100C for SKL-U # (offset at 0), because when the TCC activates at 100C, the CPU @@ -170,6 +168,8 @@ chip soc/intel/skylake device ref pcie_rp11 on end device ref pcie_rp12 on end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff |