sb/intel/i82801ix: Add common code to set up LPC IO decode ranges

This does the following:
- Add gen[1-4]_dec options to the devicetree to set up generic LPC
  decode ranges in the southbridge code.
- Move setting up some default decode ranges to a common place. If
  somehow a board needs to override this behavior it can happen in the
  mb_setup_superio() hook (that will be renamed when moving to
  C_ENVIRONMENT_BOOTBLOCK).

Change-Id: I3d904b1125bc410c11aa73a89b1969284e88dac1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

4 files changed, 6 insertions, 34 deletions

diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb
index b4c2ea89b1..9561dfa93f 100644
--- a/src/mainboard/lenovo/t400/devicetree.cb
+++ b/src/mainboard/lenovo/t400/devicetree.cb
@@ -75,6 +75,9 @@ chip northbridge/intel/gm45
 			# Maybe we should set less for Mini PCIe.
 			register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }"
 			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
+			register "gen1_dec" = "0x007c1601"
+			register "gen2_dec" = "0x000c15e1"
+			register "gen3_dec" = "0x001c1681"
 
 			device pci 19.0 on end # LAN
 			device pci 1a.0 on # UHCI
diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
index 1b763188e8..e8215654e1 100644
--- a/src/mainboard/lenovo/t400/romstage.c
+++ b/src/mainboard/lenovo/t400/romstage.c
@@ -14,16 +14,12 @@
  * GNU General Public License for more details.
  */
 
-#include <device/pci_ops.h>
 #include <console/console.h>
-#include <southbridge/intel/i82801ix/i82801ix.h>
 #include <southbridge/intel/common/gpio.h>
 #include <northbridge/intel/gm45/gm45.h>
 #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
 #include "dock.h"
 
-#define LPC_DEV PCI_DEV(0, 0x1f, 0)
-
 static void hybrid_graphics_init(sysinfo_t *sysinfo)
 {
 	bool peg, igd;
@@ -36,20 +32,6 @@ static void hybrid_graphics_init(sysinfo_t *sysinfo)
 
 static int dock_err;
 
-void mb_setup_lpc(void)
-{
-	/* Set up SuperIO LPC forwards */
-
-	/* Configure serial IRQs.*/
-	pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0);
-	/* Map COMa on 0x3f8, COMb on 0x2f8. */
-	pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
-	pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3f0f);
-	pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x7c1601);
-	pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0xc15e1);
-	pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681);
-}
-
 void mb_setup_superio(void)
 {
 	/* Minimal setup to detect dock */
diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb
index 2ed4308cfa..4efcc255ec 100644
--- a/src/mainboard/lenovo/x200/devicetree.cb
+++ b/src/mainboard/lenovo/x200/devicetree.cb
@@ -79,6 +79,9 @@ chip northbridge/intel/gm45
 			# Maybe we should set less for Mini PCIe.
 			register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }"
 			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
+			register "gen1_dec" = "0x007c1601"
+			register "gen2_dec" = "0x000c15e1"
+			register "gen3_dec" = "0x001c1681"
 
 			device pci 19.0 on end # LAN
 			device pci 1a.0 on # UHCI
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index 4382bc084d..41be94f357 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -14,25 +14,9 @@
  * GNU General Public License for more details.
  */
 
-#include <device/pci_ops.h>
 #include <southbridge/intel/common/gpio.h>
-#include <southbridge/intel/i82801ix/i82801ix.h>
 #include <northbridge/intel/gm45/gm45.h>
 
-#define LPC_DEV PCI_DEV(0, 0x1f, 0)
-
-void mb_setup_lpc(void)
-{
-	/* Configure serial IRQs.*/
-	pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0);
-	/* Map COMa on 0x3f8, COMb on 0x2f8. */
-	pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
-	pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3f0f);
-	pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x7c1601);
-	pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0xc15e1);
-	pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681);
-}
-
 void get_mb_spd_addrmap(u8 *spd_addrmap)
 {
 	spd_addrmap[0] = 0x50;