AGESA,binaryPI boards: Move IRQ table programming

IRQ programming should be done outside (obsolete) MP table
generation.

Change-Id: Ibce2af4de91549c4c9743cd997f625164672a713
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38564
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 77 insertions, 43 deletions

diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c
index bea6102cae..1a81182e55 100644
--- a/src/mainboard/lenovo/g505s/mainboard.c
+++ b/src/mainboard/lenovo/g505s/mainboard.c
@@ -6,9 +6,28 @@
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 
 #include <southbridge/amd/agesa/hudson/smi.h>
 
+static const u8 mainboard_picr_data[0x54] = {
+	0x1F, 0x1f, 0x1f, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x09, 0x1F, 0x1F, 0x0B, 0x1F, 0x0B, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x1F, 0x1F, 0x1F, 0x1F
+};
+static const u8 mainboard_intr_data[0x54] = {
+	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x10, 0x11, 0x12, 0x13
+};
+
+
 static void pavilion_cold_boot_init(void)
 {
 	/* Lid SMI is only used in non-ACPI mode; leave it off in S3 resume */
@@ -17,8 +36,16 @@ static void pavilion_cold_boot_init(void)
 	lenovo_g505s_ec_init();
 }
 
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+	intr_data_ptr = mainboard_intr_data;
+	picr_data_ptr = mainboard_picr_data;
+}
+
 static void mainboard_enable(struct device *dev)
 {
+	pirq_setup();
 
 	hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH);
 	global_smi_enable();
diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c
index 5d8eb4d3aa..3ff707d504 100644
--- a/src/mainboard/lenovo/g505s/mptable.c
+++ b/src/mainboard/lenovo/g505s/mptable.c
@@ -1,29 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/io.h>
 #include <arch/ioapic.h>
 #include <arch/smp/mpspec.h>
 #include <stdint.h>
 #include <string.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 
-u8 picr_data[0x54] = {
-	0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-	0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x1F,0x1F,0x1F,0x1F
-};
-u8 intr_data[0x54] = {
-	0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-	0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x10,0x11,0x12,0x13
-};
-
 static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
 {
 	mc->mpc_length += length;
@@ -46,7 +29,6 @@ static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;
 	int bus_isa;
-	u8 byte;
 
 	/*
 	 * By the time this function gets called, the IOAPIC registers
@@ -72,18 +54,6 @@ static void *smp_write_config_table(void *v)
 	/* I/O APICs:   APIC ID Version State   Address */
 	smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
 
-	/* PIC IRQ routine */
-	for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
-		outb(byte, 0xC00);
-		outb(picr_data[byte], 0xC01);
-	}
-
-	/* APIC IRQ routine */
-	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
-		outb(byte | 0x80, 0xC00);
-		outb(intr_data[byte], 0xC01);
-	}
-
 	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 #define IO_LOCAL_INT(type, intr, apicid, pin)				\
 	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -102,27 +72,64 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(0x0, 0x00, 0x3, 0x13);
 
 	/* Internal VGA */
-	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
-	PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+	PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+	PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
 
 	/* SMBUS */
 	PCI_INT(0x0, 0x14, 0x0, 0x10);
 
 	/* HD Audio */
-	PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+	PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
 
 	/* USB */
-	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
-	PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
-	PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
-	PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
-	PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
-	PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
-	PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+	PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
+	PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+	PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+	PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+	PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+	PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
+	PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
 
 	/* sata */
-	PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
-	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+	PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
+	PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
+
+	/* on board NIC & Slot PCIE.  */
+
+	/* PCI slots */
+	struct device *dev = pcidev_on_root(0x14, 4);
+	if (dev && dev->enabled) {
+		u8 bus_pci = dev->link_list->secondary;
+		/* PCI_SLOT 0. */
+		PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+		PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+		PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+		PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+		/* PCI_SLOT 1. */
+		PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+		PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+		PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+		PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+		/* PCI_SLOT 2. */
+		PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+		PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+		PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+		PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+	}
+
+	/* PCIe Lan*/
+	PCI_INT(0x0, 0x06, 0x0, 0x13);
+
+	/* FCH PCIe PortA */
+	PCI_INT(0x0, 0x15, 0x0, 0x10);
+	/* FCH PCIe PortB */
+	PCI_INT(0x0, 0x15, 0x1, 0x11);
+	/* FCH PCIe PortC */
+	PCI_INT(0x0, 0x15, 0x2, 0x12);
+	/* FCH PCIe PortD */
+	PCI_INT(0x0, 0x15, 0x3, 0x13);
 
 	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 	IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);