diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-25 14:03:40 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-28 08:52:37 +0000 |
| commit | 9f78127b61632cbb138bdbfa650c2e9965440d3b (patch) | |
| tree | b0f146a3725bcd86b83242b9abb465bd27829681 /src/mainboard/lenovo | |
| parent | 172bcc835f0d214444398c57a0ca9eddd2941ecf (diff) | |
lynxpoint: Factor out PIRQ routing from devicetree
All boards disable PIRQs. They aren't used on modern OSes anyway.
Change-Id: I1351fd4a3910e8cf2e9afe51dc2e82c7464de403
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/lenovo')
| -rw-r--r-- | src/mainboard/lenovo/t440p/devicetree.cb | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index e8f8a1a396..60728c496c 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -38,14 +38,6 @@ chip northbridge/intel/haswell register "gen4_dec" = "0x000c06a1" register "gpi13_routing" = "2" register "gpi1_routing" = "2" - register "pirqa_routing" = "0x80" - register "pirqb_routing" = "0x80" - register "pirqc_routing" = "0x80" - register "pirqd_routing" = "0x80" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" register "sata_ahci" = "1" # 0(HDD), 1(M.2), 5(ODD) register "sata_port_map" = "0x23" |