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authorSven Schnelle <svens@stackframe.org>2011-02-21 09:39:17 +0000
committerSven Schnelle <svens@stackframe.org>2011-02-21 09:39:17 +0000
commit541269bc85b7d63b7660cd299e70335a52d5fdf4 (patch)
tree5494ba16137a9830a8a5a9bb3ccd5c856f7962e6 /src/mainboard/lenovo
parent0c8e664713d4dc726bedb5ba0b2e356eed9ae14c (diff)
[i945] Add SPD adress mapping
The current code works only with dual channel if Channel 0 uses SPD address 0x50/0x51, while the second channel has to use 0x52/0x53. For hardware that uses other addresses (like the ThinkPad X60) this means we get only one module running instead of both. This patch adds a second parameter to sdram_initialize, which is an array with 2 * DIMM_SOCKETS members. It should contain the SPD addresses for every single DIMM socket. If NULL is given as the second parameter, the code uses the old addressing scheme. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6374 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/lenovo')
-rw-r--r--src/mainboard/lenovo/x60/romstage.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 5578324055..e2b4a402a5 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -294,6 +294,7 @@ void main(unsigned long bist)
{
u32 reg32;
int boot_mode = 0;
+ const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 };
if (bist == 0)
enable_lapic();
@@ -357,7 +358,7 @@ void main(unsigned long bist)
dump_spd_registers();
#endif
- sdram_initialize(boot_mode);
+ sdram_initialize(boot_mode, spd_addrmap);
/* Perform some initialization that must run before stage2 */
early_ich7_init();