nb/intel/raminit (native): Read PCI mmio size from devicetree

Instead of hardcoding the PCI mmio size read it from devicetree.
Set a default value of 2048 MiB and 1024MiB for laptops without
discrete graphics.

Tested on Sandybridge Lenovo T520.

Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15140
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

10 files changed, 20 insertions, 0 deletions

diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb
index 7923046e49..43a610ab5f 100644
--- a/src/mainboard/lenovo/t400/devicetree.cb
+++ b/src/mainboard/lenovo/t400/devicetree.cb
@@ -23,6 +23,8 @@ chip northbridge/intel/gm45
 		end
 	end
 
+	register "pci_mmio_size" = "2048"
+
 	device domain 0 on
 		device pci 00.0 on
 			subsystemid 0x17aa 0x20e0
diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb
index 9f42cbb9b3..809e3eed22 100644
--- a/src/mainboard/lenovo/t420/devicetree.cb
+++ b/src/mainboard/lenovo/t420/devicetree.cb
@@ -36,6 +36,8 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
+	register "pci_mmio_size" = "2048"
+
 	device domain 0 on
 		device pci 00.0 on
 			subsystemid 0x17aa 0x21ce
diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb
index 2376d64bea..841e6753d1 100644
--- a/src/mainboard/lenovo/t420s/devicetree.cb
+++ b/src/mainboard/lenovo/t420s/devicetree.cb
@@ -35,6 +35,8 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
+	register "pci_mmio_size" = "2048"
+
 	device domain 0 on
 		device pci 00.0 on
 			subsystemid 0x17aa 0x21d2
diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb
index 8c0f10f9ba..d1cea3cc06 100644
--- a/src/mainboard/lenovo/t430s/devicetree.cb
+++ b/src/mainboard/lenovo/t430s/devicetree.cb
@@ -35,6 +35,8 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
+	register "pci_mmio_size" = "2048"
+
 	device domain 0 on
 		device pci 00.0 on
 			subsystemid 0x17aa 0x21fb
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index 379a95d3af..c0292ec3fd 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -36,6 +36,8 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
+	register "pci_mmio_size" = "2048"
+
 	device domain 0 on
 		device pci 00.0 on end # host bridge
 		device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M]
diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb
index 7db65c73ba..43d8264e3d 100644
--- a/src/mainboard/lenovo/t530/devicetree.cb
+++ b/src/mainboard/lenovo/t530/devicetree.cb
@@ -36,6 +36,8 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
+	register "pci_mmio_size" = "2048"
+
 	device domain 0 on
 		device pci 00.0 on end # host bridge
 		device pci 01.0 on end # PCIe Bridge for discrete graphics
diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb
index 92c41d73d9..9f5bb41577 100644
--- a/src/mainboard/lenovo/x200/devicetree.cb
+++ b/src/mainboard/lenovo/x200/devicetree.cb
@@ -28,6 +28,8 @@ chip northbridge/intel/gm45
 		end
 	end
 
+	register "pci_mmio_size" = "1024"
+
 	device domain 0 on
 		device pci 00.0 on
 			subsystemid 0x17aa 0x20e0
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb
index 23745540f8..bd6490e889 100644
--- a/src/mainboard/lenovo/x201/devicetree.cb
+++ b/src/mainboard/lenovo/x201/devicetree.cb
@@ -80,6 +80,8 @@ chip northbridge/intel/nehalem
 		end
 	end
 
+	register "pci_mmio_size" = "1024"
+
 	device domain 0 on
 		device pci 00.0 on # Host bridge
 			subsystemid 0x17aa 0x2193
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb
index 6f84acd00a..af70b2021e 100644
--- a/src/mainboard/lenovo/x220/devicetree.cb
+++ b/src/mainboard/lenovo/x220/devicetree.cb
@@ -36,6 +36,8 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
+	register "pci_mmio_size" = "1024"
+
 	device domain 0 on
 		device pci 00.0 on
 			subsystemid 0x17aa 0x21db
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
index 37d53d4492..f0c940d736 100644
--- a/src/mainboard/lenovo/x230/devicetree.cb
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -36,6 +36,8 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
+	register "pci_mmio_size" = "1024"
+
 	device domain 0 on
 		device pci 00.0 on
 			subsystemid 0x17aa 0x21fa