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authorVladimir Serbinenko <phcoder@gmail.com>2014-01-09 11:13:18 +0100
committerVladimir Serbinenko <phcoder@gmail.com>2014-01-23 19:56:52 +0100
commitbca985557e3a7dc94c954d7295a963f654886a08 (patch)
treed3504e6930d0e8dcd343a60f80f664bdf6239443 /src/mainboard/lenovo
parentf7a42de725b2e5a2a7e3af7cee61291c56cd6518 (diff)
X201: Move early nehalem S3 magic to right place.
This MCH magic needs to be done before GPIO. Now S3 (Suspend-to-RAM) works on X201. Change-Id: I319e57af52ff01083bfbffbcd883ac5f453320a1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4632 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/lenovo')
-rw-r--r--src/mainboard/lenovo/x201/romstage.c12
1 files changed, 3 insertions, 9 deletions
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 3edf9fba86..57e1e505a0 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -240,25 +240,19 @@ void main(unsigned long bist)
if (bist == 0)
enable_lapic();
- /* Force PCIRST# */
- pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
- pci_write_config16(PCI_DEV(0, 0, 0), BCTRL, SBR);
- udelay(200 * 1000);
- pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
- pci_write_config16(PCI_DEV(0, 0, 0), BCTRL, 0);
+ nehalem_early_initialization(NEHALEM_MOBILE);
+
+ pch_enable_lpc();
/* Enable USB Power. We need to do it early for usbdebug to work. */
ec_set_bit(0x3b, 4);
- pch_enable_lpc();
-
/* Enable GPIOs */
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&x201_gpio_map);
- nehalem_early_initialization(NEHALEM_MOBILE);
/* This should probably go away. Until now it is required
* and mainboard specific