diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-15 22:02:28 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-11-12 14:06:37 +0000 |
| commit | b9d2589ca40026b543ecb5b008ce0d1bc346bf53 (patch) | |
| tree | 87cac45cfc1c1211f012aaa76b8a87162f092aff /src/mainboard/lenovo/z61t/devicetree.cb | |
| parent | 81dd52b7eb663c6098de5d8c7c56ed572c91b539 (diff) | |
mb/*/*: Harmonise FD and devicetree on boards featuring ICH7
On some boards the devicetree and Function Disable register did not
match. In this case the FD values are put in the devicetree as these
were the values that were actually used in practice.
A complete devicetree will make it easier to automatically disable
devices in ramstage.
Change-Id: I1692ca5f490ea84e2fc520d3f66044ad7514f76e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/lenovo/z61t/devicetree.cb')
| -rw-r--r-- | src/mainboard/lenovo/z61t/devicetree.cb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/z61t/devicetree.cb b/src/mainboard/lenovo/z61t/devicetree.cb index 1c60e6bf6b..92bf3cec85 100644 --- a/src/mainboard/lenovo/z61t/devicetree.cb +++ b/src/mainboard/lenovo/z61t/devicetree.cb @@ -97,6 +97,9 @@ chip northbridge/intel/i945 device pci 1c.3 on # PCI Express Port 4 subsystemid 0x17aa 0x2011 end + device pci 1c.4 off end # PCIe port 5 + device pci 1c.5 off end # PCIe port 6 + device pci 1d.0 on # USB UHCI subsystemid 0x17aa 0x200a end @@ -122,6 +125,8 @@ chip northbridge/intel/i945 end end + device pci 1e.2 off end # AC'97 Audio + device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # PCI-LPC bridge subsystemid 0x17aa 0x2009 chip ec/lenovo/pmh7 |