soc/intel/tgl: Enable USB4 resources based on common Kconfig

Intel TGL BIOS specification (doc ##611569) Revision 0.7.6 Section
7.2.5.1.5 recommends reserving the following resources for each PCIe
USB4 root port:

 - 42 buses
 - 194 MiB Non-prefetchable memory
 - 448 MiB Prefetchable memory

This change enables reserving of resources for USB4 when mainboard
selects the newly added Kconfig SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES.

This is similar to the change for ADL in commit 8d11cdc6fa
("soc/intel/alderlake: Add Kconfig for recommended PCIe TBT resources").

Change-Id: I25ec3f74ebd5727fa4b13f5a3b11050f77ecb008
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

0 files changed, 0 insertions, 0 deletions