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authorVladimir Serbinenko <phcoder@gmail.com>2014-10-28 23:43:20 +0100
committerVladimir Serbinenko <phcoder@gmail.com>2014-11-19 21:09:51 +0100
commit36fa5b80843d836518eb89f46747e80ed6b5d96f (patch)
treea36f498a48aaa8764df768ff3616ff476f62a07b /src/mainboard/lenovo/x230/devicetree.cb
parent10dd0e3171bc631fd5d83d4f42aa376edd3c6d55 (diff)
i82801ix,bd82x6x,ibexpeak: rewrite expresscard hotplug
This implementation is more compact, unified and works with windows as well. Tested under windows and under Debian GNU/Linux. Change-Id: I585dec12e17e22d829baa3f2dc7aecc174f9d3b5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7296 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/lenovo/x230/devicetree.cb')
-rw-r--r--src/mainboard/lenovo/x230/devicetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
index 256586bf40..c44a2b7a1a 100644
--- a/src/mainboard/lenovo/x230/devicetree.cb
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -74,6 +74,8 @@ chip northbridge/intel/sandybridge
register "gen2_dec" = "0x0c15e1"
register "gen4_dec" = "0x0c06a1"
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
+
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported