Lenovo X230: new port

probably a problem in MRC:
- EHCI output failure after sysagent
- no S3
- no MRC cache
- MRC needs watchdog
- less MTRR could be used by some memory map optimisations

Not tested:
- dock (probably doesn't work)
- msata (probably works)
- wwan (probably works)
- mini displayport (probably works)

Blobs:
MRC
VGA Oprom

Change-Id: I5bdb9372971f48e048848d57b6c924b79782dbde
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4679
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

7 files changed, 294 insertions, 0 deletions

diff --git a/src/mainboard/lenovo/x230/acpi/ec.asl b/src/mainboard/lenovo/x230/acpi/ec.asl
new file mode 100644
index 0000000000..4b3e72cb03
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/ec.asl
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <ec/lenovo/h8/acpi/ec.asl>
+
+Scope(\_SB.PCI0.LPCB.EC)
+{
+}
diff --git a/src/mainboard/lenovo/x230/acpi/gpe.asl b/src/mainboard/lenovo/x230/acpi/gpe.asl
new file mode 100644
index 0000000000..eb489d5c4e
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/gpe.asl
@@ -0,0 +1,13 @@
+	Method (_L01, 0, NotSerialized)
+	{
+		If (\_SB.PCI0.RP03.HPCS)
+		{
+			Sleep (100)
+			Store (0x01, \_SB.PCI0.RP03.HPCS)
+			If (\_SB.PCI0.RP03.PDC)
+			{
+				Store (0x01, \_SB.PCI0.RP03.PDC)
+				Notify (\_SB.PCI0.RP03, 0x00)
+			}
+		}
+	}
diff --git a/src/mainboard/lenovo/x230/acpi/mainboard.asl b/src/mainboard/lenovo/x230/acpi/mainboard.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/mainboard.asl
diff --git a/src/mainboard/lenovo/x230/acpi/platform.asl b/src/mainboard/lenovo/x230/acpi/platform.asl
new file mode 100644
index 0000000000..73478eae7d
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/platform.asl
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	/* Not implemented.  */
+	Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000000..ba725ac1db
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },//              GFX    INTA -> PIRQA (MSI)
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 16 },//  D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 17 },//  D28IP_P1IP  WLAN   INTA -> PIRQB
+			Package() { 0x001cffff, 1, 0, 21 },//  D28IP_P2IP  ETH0   INTB -> PIRQF
+			Package() { 0x001cffff, 2, 0, 19 },//  D28IP_P3IP  SDCARD INTC -> PIRQD
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },//  D29IP_E1P   EHCI1  INTA -> PIRQD
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 21 },//  D26IP_E2P   EHCI2  INTA -> PIRQF
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP   SATA   INTA -> PIRQB (MSI)
+			Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP  SMBUS  INTB -> PIRQH
+			Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP  THRT   INTC -> PIRQA
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+		})
+	}
+}
+
diff --git a/src/mainboard/lenovo/x230/acpi/superio.asl b/src/mainboard/lenovo/x230/acpi/superio.asl
new file mode 100644
index 0000000000..a2657f1eff
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/superio.asl
@@ -0,0 +1 @@
+#include "../../../../drivers/pc80/ps2_controller.asl"
diff --git a/src/mainboard/lenovo/x230/acpi/video.asl b/src/mainboard/lenovo/x230/acpi/video.asl
new file mode 100644
index 0000000000..12a268b39d
--- /dev/null
+++ b/src/mainboard/lenovo/x230/acpi/video.asl
@@ -0,0 +1,115 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
+ * Copyright (c) 2013 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "smi.h"
+
+Scope (\_SB.PCI0.GFX0)
+{
+	Device (LCD0)
+	{
+		Name (_ADR, 0x0400)
+		Name (BRCT, 0)
+
+		Name (BRIG, Package (0x12)
+		{
+			0x61,
+			0x61,
+			0x2,
+			0x4,
+			0x5,
+			0x7,
+			0x9,
+			0xb,
+			0xd,
+			0x11,
+			0x14,
+			0x17,
+			0x1c,
+			0x20,
+			0x27,
+			0x31,
+			0x41,
+			0x61,
+		})
+
+		Method (_BCL, 0, NotSerialized)
+		{
+			Store (1, BRCT)
+			Return (BRIG)
+		}
+
+		Method (_BCM, 1, NotSerialized)
+		{
+			Store (ShiftLeft (Arg0, 4), ^^BCLV)
+			Store (0x80000000, ^^CR1)
+			Store (0x061a061a, ^^CR2)
+		}
+		Method (_BQC, 0, NotSerialized)
+		{
+			Store (^^BCLV, Local0)
+			ShiftRight (Local0, 4, Local0)
+			Return (Local0)
+		}
+
+		Method(BRID, 1, NotSerialized)
+		{
+			Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0)
+			If (LEqual (Local0, Ones))
+			{
+				Return (0x11)
+			}
+			Return (Local0)
+		}
+
+		/* Using Notify is the right way. But Windows doesn't handle
+		   it well. So use both method in a way to avoid double action.
+		 */
+		Method (DECB, 0, NotSerialized)
+		{
+			If (BRCT)
+			{
+				Notify (LCD0, 0x87)
+			} Else {
+				Store (BRID (_BQC ()), Local0)
+				If (LNotEqual (Local0, 2))
+				{
+					Decrement (Local0)
+				}
+				_BCM (DerefOf (Index (BRIG, Local0)))
+			}
+		}
+		Method (INCB, 0, NotSerialized)
+		{
+			If (BRCT)
+			{
+				Notify (LCD0, 0x86)
+			} Else {
+				Store (BRID (_BQC ()), Local0)
+				If (LNotEqual (Local0, 0x11))
+				{
+					Increment (Local0)
+				}
+				_BCM (DerefOf (Index (BRIG, Local0)))
+			}
+		}
+	}
+}