diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-05-04 14:19:32 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-08 10:31:23 +0000 |
| commit | 62bc1cb88ba0103189f6c1c957207c9520986043 (patch) | |
| tree | 36f07a62e38229ac85016251d202e51c4087e892 /src/mainboard/lenovo/x220/vboot-rwa.fmd | |
| parent | 25212117534f0cb29939a7fc6c1271ca0fa083cd (diff) | |
mb/lenovo/*: Add support for VBOOT on 8MiB devices
Enable VBOOT support on all devices that have a 8 MiB flash, using a
single RW_MAIN_A partition, allowing the use of tianocore payload in
both RW_MAIN_A and WP_RO.
* Add VBNV section to cmos.layout
* Add FMAP for VBOOT and regular boot
* Select Kconfigs for VBOOT
* Enable VBOOT_SLOTS_RW_A by default
Also build test VBOOT on Lenovo T420.
Tested on Lenovo T520 using Icb7b263ed86551cc53e1db7babccaca6b3ae2fe6.
Change-Id: Icb7b263ed86551cc53e1db7babccaca6b3ae2fe6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/lenovo/x220/vboot-rwa.fmd')
| -rw-r--r-- | src/mainboard/lenovo/x220/vboot-rwa.fmd | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/x220/vboot-rwa.fmd b/src/mainboard/lenovo/x220/vboot-rwa.fmd new file mode 100644 index 0000000000..8a4cd3b477 --- /dev/null +++ b/src/mainboard/lenovo/x220/vboot-rwa.fmd @@ -0,0 +1,29 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x300000 { + RW_SECTION_A@0x00000 0x180000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x180000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x1a0000 0x1000 + SMMSTORE(PRESERVE)@0x1a1000 0x40000 + + WP_RO@0x1e1000 0x11f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0xff000 + } + } +} |