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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-04-05 12:05:12 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2017-04-07 08:58:22 +0200 |
| commit | 7dee97454a7391d61080e0ff689ee207ae41dacc (patch) | |
| tree | b6d8586895fd533a2513be09a209368ed45d6e00 /src/mainboard/lenovo/x201/romstage.c | |
| parent | 5995ee62f725cb06f7ed9b1f3f6df89078cff065 (diff) | |
mb/lenovo/x201: Link gpio map instead of including a header
Linking should allow to link depending on possible future variants.
E.g. in Makefile.inc romstage-$(CONFIG_'VARIANT0') += gpio_variant0.c
etc.
Change-Id: I88b5ef8e12ac606751952a493f626e1b146e98f7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19139
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/lenovo/x201/romstage.c')
| -rw-r--r-- | src/mainboard/lenovo/x201/romstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 107cc46fc8..7634de8e98 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -37,10 +37,10 @@ #include <cbmem.h> #include <tpm.h> -#include "gpio.h" #include "dock.h" #include "arch/early_variables.h" #include <southbridge/intel/ibexpeak/pch.h> +#include <southbridge/intel/common/gpio.h> #include <northbridge/intel/nehalem/nehalem.h> #include <northbridge/intel/nehalem/raminit.h> @@ -200,7 +200,7 @@ void mainboard_romstage_entry(unsigned long bist) pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - setup_pch_gpios(&x201_gpio_map); + setup_pch_gpios(&mainboard_gpio_map); /* This should probably go away. Until now it is required |